VLSI Based New Pipelined Architecture Design for Radix-2 FFT

Abstract

Improvements of wireless digital communication application have large demands on Signal Processing operations. Frequency transformation techniques are recognized as high potential in the field of digital communication. In this study, a new pipelined based Fast Fourier Transformation (FFT) architecture is designed for performing frequency transformation techniques. Delay Feedback (DF) and Delay Commutator (DC) based structures are widely used to perform frequency transformation techniques. A new architecture called “Single path Delay Commutator (SDC)” is introduced in this study to estimate the frequency representation of discrete time input samples. Further, Single path Delay Feedback (SDF) structures are utilized in the final stage of SDC architecture for obtaining response in bit reversing order. Proposed new architecture is named as “Radix-2 Mixed SDC-SDF FFT” To increase the processing speed of FFT architectures, pipelining techniques is introduced in the proposed Mixed SDC-SDF FFT architecture. Hence, the proposed new architecture named as “Pipelined Radix-2 Mixed SDC-SDF FFT”. The performance evaluation of proposed architecture is determined through Very Large Scale Integration (VLSI) System design environment. Less area utilization, low power consumption and high speed are the main concerns in VLSI System design environment. Hence, the aim of proposed new architecture is to reduce the hardware architecture, power consumption and increasing both speed and throughput of the system. Proposed new Pipelined Radix-2 Mixed SDC-SDF FFT architecture offers 17.6% reduction of Slices, 21.65% reduction of LUTs, 45.92% reduction of maximum combinational delay and 24.22% reduction of power consumption than best existing Radix-2 SDF FFT structure.