A Novel VLSI Based Radix-2 Single Path Delay Commutator (R2SDC) FFT Architecture Design

Abstract

The aim is to design a new architecture called Novel Radix-2 Single path Delay Commutator (R2SDC) for improving the architectural performances of Fast Fourier Transformation (FFT) technique. In proposed new architecture, only commutator structures and complex multipliers are used to convert the time domain signals into frequency domain signals. In order to match the frequency response, delay elements are used appropriately. Traditional pipelined architectures have multiple complex multiplication units for performing frequency transformation techniques. But, proposed R2SDC structure has single complex multiplication unit per stage. Data flow structures of R2SDC architecture has been designed through Very Large Scale Integration (VLSI) System design environment. Proposed novel architecture called R2SDC FFT offers 21.4% improvements in hardware slices, 26.76% improvements in Look Up Tables (LUTs), 23.49% improvements in maximum output required time after clock and 31.88% improvements in power consumptions than traditional pipelined Radix-2 Single path Delay Feedback (R2SDF) FFT architecture. Also proposed architecture offers 4.61% improvements in hardware slices, 6.52% improvements in LUTs and 10.10% improvements in power consumption than combined SDC-SDF FFT architecture. In future, proposed R2DSC FFT architecture will be useful in Orthogonal Frequency Division Multiplexing (OFDM) architecture for estimating the frequency response of digital signals. It will be useful in large distance communications based applications