Positive Gate Bias Stress Research Articles

High-Performance Amorphous InGaZnO Thin Film Transistor With High-k Van Der Waals Molecular Dielectric

We report the amorphous Indium-Gallium-Zinc-Oxide (In:Ga:Zn = 2.8:9.6:1) thin film transistors (TFTs) using an inorganic molecular insulating dielectric of antimony trioxide (Sb2O3). Due to dangling-bond-free interface nature of the van der Waals (vdW) bonded interaction, the TFTs show robustly enhanced field-effect mobility ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu _{\!\textit {FE}}$ </tex-math></inline-formula> ) up to 45 cm2V−1s−1, in addition with occurance of bandlike transport. Importantly, ideal onset speed with subthreshold swing (SS) down to 70 mV/dec was achieved, demonstrating the suppression of interface defects which can be further illustrated by the superior bias stress stability under positive gate-bias stress (PBS), with only 12 mV threshold voltage shift at applying gate bias with 3 V for 4000 s. The homogeneous performance of a series of devices processed exhibit excellent stability and reliability.

Improved Stability With Atomic-Layer-Deposited Encapsulation on Atomic-Layer In2O3 Transistors by Reliability Characterization

Ultrathin In2O3 and other recently explored low-thermal-budget ultrathin oxide semiconductors have shown great promise for back-end-of-line (BEOL)-compatible logic layers and monolithic 3-D (M3-D) integration. However, the long-term stability and reliability of these defect-rich atomically thin channels have not been intensively explored yet. Here, we present a study of the long-term reliability of transistors with 1.2-nm-thick atomic-layer-deposited (ALD)-grown In2O3 channels by room-temperature positive bias instability (PBI) and negative bias instability (NBI) experiments. The observed behavior can be largely explained by a trap neutrality level (TNL) model. A route to reduce the parameter drift has been developed using encapsulation in sequence with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{T}$ </tex-math></inline-formula> engineering by an O2 plasma treatment. After treatment, the magnitude of long-term <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{T}$ </tex-math></inline-formula> shift is reduced for both positive and negative gate bias stresses, and for negative bias stress, other transistor parameters are stabilized as well. In all cases, the subthreshold swing (SS) does not change over time, suggesting that stress-induced interface defects form far below the conduction band, if at all.

Improvement in Short-Channel Effects of the Thin-Film Transistors Using Atomic-Layer Deposited In–Ga–Sn–O Channels With Various Channel Compositions

In–Ga–Sn–O (IGTO) thin-film transistors (TFTs) were fabricated with channel lengths from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3 \mu \text{m}$ </tex-math></inline-formula> to 500 nm to investigate the short-channel effects (SCEs), in which IGTO channel compositions were modulated during the atomic-layer deposition. The SCEs appearing in the IGTO TFTs were found to be manifested by increasing the In/Ga ratio of IGTO channel, showing typical channel composition dependence. Alternatively, small values of the channel-length reduction and contact resistance could be obtained to be 50 nm and 0.52 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{k}\Omega $ </tex-math></inline-formula> , respectively, for the device using the IGTO channel with an In/Ga ratio of 1.7. Threshold voltage shifts of the IGTO TFT were estimated to be only +0.03 and +1.22 V under negative and positive gate-bias stress for 104 s, respectively, even with a channel length as short as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1 \mu \text{m}$ </tex-math></inline-formula> .

Threshold voltage reliability in flexible amorphous In–Ga–ZnO TFTs under simultaneous electrical and mechanical stress

Flexible amorphous In–Ga–ZnO (a-IGZO) thin film transistors (TFTs) have been successfully demonstrated on 50 µm thick freestanding polyimide (PI) with µ sat around 10 cm2 V−1 s−1. In the literature, common characterization of flexible TFTs consist of measuring their electrical response at different bending radius or under positive and negative gate bias stress (PBS and NBS). However, there are few studies where the flexible TFTs have been measured with a simultaneous mechanical and electrical stress. In this work, simultaneous testing under electrical and mechanical stress were carried out with a gate bias stress voltage of ±6 V during 3600 s, and with a tensile bending radius of 1, 2 and 4 mm. a-IGZO TFTs bottom gate-top contacts were fabricated on commercial Kapton HN PI by a complete photolithography process. All the PBS and NBS characteristics presented an abnormal threshold voltage left shift which was mainly explained by the adsorption/desorption of water molecules at the back channel. This V th shift was modeled with the stretched exponential equation. Analyzed TFTs were stable under simultaneous stress until a 4 mm bending radius with electrical parameters V th, subthreshold slope, µ sat and I on/I off in the order of 0.7 V, 340 mV dec−1, 6 cm2 V−1 s−1 and 5 × 108, respectively.

Structural Engineering Effects on Hump Characteristics of ZnO/InSnO Heterojunction Thin-Film Transistors.

Transparent conductive oxides (TCO) have been extensively investigated as channel materials for thin-film transistors (TFTs). In this study, highly transparent and conductive InSnO (ITO) and ZnO films were deposited, and their material properties were studied in detail. Meanwhile, we fabricated ZnO/ITO heterojunction TFTs, and explored the effects of channel structures on the hump characteristics of ZnO/ITO TFTs. We found that Vhump–VON was negatively correlated with the thickness of the bottom ZnO layer (10, 20, 30, and 40 nm), while it was positively correlated with the thickness of the top ITO layer (3, 5, 7, and 9 nm), where Vhump is the gate voltage corresponding to the occurrence of the hump and VON is the turn-on voltage. The results demonstrated that carrier transport forms dual current paths through both the ZnO and ITO layers, synthetically determining the hump characteristics of the ZnO/ITO TFTs. Notably, the hump was effectively eliminated by reducing the ITO thickness to no more than 5 nm. Furthermore, the hump characteristics of the ZnO/ITO TFTs under positive gate-bias stress (PBS) were examined. This work broadens the practical application of TCO and provides a promising method for solving the hump phenomenon of oxide TFTs.

Optimization of Dual-Fuel Combustion Synthesis for Rapid Formation of Solution-Processed Metal-Oxide Thin-Film Transistors

Solution processing of metal-oxide semiconductors has received significant attention in various fields of electronics owing to its advantages such as simple fabrication process, large-area scalability, and facile stoichiometric tunability. However, the conventional sol–gel route requires a relatively long annealing time to obtain a low-defect film with high density and sufficient amount of metal–oxygen–metal bonding state, which prevents implementation in cost-effective continuous manufacturing. Here, we report rapid formation of solution-processed oxide semiconductors by employing a dual-fuel-based solution combustion synthesis route. In particular, by optimizing the ratio of dual fuels of acetylacetone and 1,1,1-trifluoro-acetylacetone (molar ratio of 7:3), high-performance indium–gallium–zinc oxide (IGZO) thin-film transistors (TFTs) could be fabricated at 350 °C with the annealing time as short as 5 min (In:Ga:Zn = 0.68:0.1:0.22). Based on spectroscopic analysis, it was found that the dual fuels enabled rapid formation of the metal–oxygen–metal lattice structure with low defective oxygen bonding states. The IGZO TFTs fabricated with an optimized fuel ratio exhibited average field-effect mobilities of 1.11 and 3.69 cm2 V–1 s–1 with annealing times of 5 and 20 min, respectively (averaged in 9∼12 devices). Also, in the case of the 5 min annealed device, the threshold voltage was −0.48 ± 1.96 V, showing enhancement-mode operation. Furthermore, the device showed good stability against both positive gate bias stress and negative gate bias stress conditions with small threshold voltage shifts of −1.28 and – 1.28 V in 5760 s, respectively.

Characterization of optimized properties for InGaZnO semiconductor and thin film transistor by oxygen partial pressure

The InGaZnO thin films with varied the O2 flow ratios were deposited by a magnetron sputtering system. The effect of O2 content on the structure, surface morphology, optical and electrical properties of InGaZnO thin films is studied. Then, we investigate the relationship between bias stress stability and density of states (DOS) of thin film transistors (TFTs) with various oxygen partial pressure InGaZnO (IGZO) as the channel layer. The temperature-dependent field-effect measurements are used to calculate DOS of IGZO TFTs. With the increase of the oxygen partial pressure, the value of DOS decreases from 2.2 × 1016 to 5.5 × 1015 cm-3. Moreover, the positive gate bias stress of IGZO TFTs are investigated. Under positive gate bias stress, the transfer curves of IGZO TFTs with various oxygen partial pressure show an obvious shift, the value of threshold voltage shift () is 5.1, 2.94, 2 and 0.8 V, respectively. The results suggest that the device with a smaller DOS is more stable than others. Therefore, this study offers a brief and accurate method to demonstrate instability mechanism of IGZO TFTs.

Ultrathin Al‐Assisted Al2O3 Passivation Layer for High‐Stability Tungsten Diselenide Transistors and Their Ambipolar Inverter

Abstract2D transition metal dichalcogenides (TMDs) have recently received significant attention owing to their superior electrical, optical, and mechanical properties. However, most previous research on TMDs has not focused on their stability against bias and illumination stress. Here, high‐stability tungsten diselenide (WSe2) field‐effect transistors (FETs) are introduced with an ultrathin Al‐assisted alumina (Al2O3) passivation. Through the Al‐assisted Al2O3 passivation, the transport behavior of the WSe2 FETs is converted from p‐type to ambipolar owing to the n‐type doping effect of Al2O3 passivation. Furthermore, the stability of the WSe2 FETs is highly improved against gate bias and illumination stress owing to the effect of Al2O3 film quality on WSe2 by ultrathin Al predeposition (≈1 nm). To compare the stress effect on the electrical characteristics, three types of devices: 1) pristine WSe2 FETs, 2) WSe2 FET with Al2O3 passivation layer, and 3) WSe2 FETs with Al‐assisted Al2O3 passivation layer, are systematically tested with positive gate bias stress (PBS) and positive gate bias illumination stress (PBIS). Finally, an ambipolar inverter composed of Al‐assisted Al2O3 passivated WSe2 FETs is demonstrated. This study proposes a promising approach that improves the stability of TMD‐based FETs for next‐generation logic applications.

Effect of HfO2-Based Multi-Dielectrics on Electrical Properties of Amorphous In-Ga-Zn-O Thin Film Transistors

We report the fabrication of bottom gate a-IGZO TFTs based on HfO2 stacked dielectrics with decent electrical characteristics and bias stability. The microscopic, electrical, and optical properties of room temperature deposited a-IGZO film with varied oxygen content were explored. In order to suppress the bulk defects in the HfO2 thin film and hence maximize the quality, surface modification of the SiNx film was investigated so as to achieve a more uniform layer. The root mean square (RMS) roughness of SiNx/HfO2/SiNx (SHS) stacked dielectrics was only 0.66 nm, which was reduced by 35% compared with HfO2 single film (1.04 nm). The basic electrical characteristics of SHS-based a-IGZO TFT were as follows: Vth is 2.4 V, μsat is 21.1 cm2 V−1 s−1, Ion/Ioff of 3.3 × 107, Ioff is 10−11 A, and SS is 0.22 V/dec. Zr-doped HfO2 could form a more stable surface, which will decrease the bulk defect states so that the stability of device can be improved. It was found that the electrical characteristics were improved after Zr doping, with a Vth of 1.4 V, Ion/Ioff of 108, μsat of 19.5 cm2 V−1 s−1, Ioff of 10−12 A, SS of 0.18 V/dec. After positive gate bias stress of 104 s, the ΔVth was decreased from 0.43 V (without Zr doping) to 0.09 V (with Zr doping), the ΔSS was decreased from 0.19 V/dec to 0.057 V/dec, respectively, which shows a meaningful impact to realize the long-term working stability of TFT devices.

Role of in-situ hydrogen plasma treatment on gate bias stability and performance of a-IGZO thin-film transistors

This work investigates the effect of an in situ hydrogen plasma treatment on gate bias stability and performance of amorphous InGaZnO thin-film transistors (TFTs) deposited by using atmospheric-pressure PECVD. The H2 plasma-treated a-IGZO channel has shown significant improvement in bias stress induced instability with a minuscule threshold voltage shift (ΔV th) of 0.31 and −0.17 V under positive gate bias stress (PBS) and negative gate bias stress (NBS), respectively. With the aid of the energy band diagram, the proposed work demonstrates the formation of negative species O2 − and positive species H2O+ in the backchannel under PBS and NBS in addition to ionized oxygen vacancy (Vo) defects at a-IGZO/ZrO2 interfaces are the reason for gate bias instability which could be effectively suppressed with in situ H2 plasma treatment. From the experimental result, it is observed that the electrical performance such as field-effect mobility (μ FE), on-off current ratio (I on/I off), and subthreshold swing improved significantly by in situ H2 plasma treatment with passivation of interface trap density and bulk trap defects.

High-Performance Indium Gallium Tin Oxide Transistors with an Al2O3 Gate Insulator Deposited by Atomic Layer Deposition at a Low Temperature of 150 °C: Roles of Hydrogen and Excess Oxygen in the Al2O3 Dielectric Film.

In this work, high-performance amorphous In0.75Ga0.23Sn0.02O (a-IGTO) transistors with an atomic layer-deposited Al2O3 dielectric layer were fabricated at a maximum processing temperature of 150 °C. Hydrogen (H) and excess oxygen (Oi) in the Al2O3 film, which was controlled by adjusting the oxygen radical density (PO2: flow rate of O2/[Ar+O2]) in the radio-frequency (rf) plasma during ALD growth of Al2O3, significantly affected the performance and stability of the resulting IGTO transistors. The concentrations of H and Oi in Al2O3/IGTO stacks according to PO2 were characterized by secondary ion mass spectroscopy, X-ray photoelectron spectroscopy, hard X-ray photoemission spectroscopy, and thermal desorption spectroscopy. The high concentration of H at a low PO2 of 2.5% caused heavy electron doping in the underlying IGTO during thermal annealing at 150 °C, leading to a conductive behavior in the resulting transistor without modulation capability. In contrast, a high PO2 condition of 20% introduced O2 molecules (or Oi) into the Al2O3 film, which negatively impacted the carrier mobility and caused anomalous photo-bias instability in the IGTO transistor. Through in-depth understanding of how to manipulate H and Oi in Al2O3 by controlling the PO2, we fabricated high-performance IGTO transistors with a high field-effect mobility (μFE) of 58.8 cm2/Vs, subthreshold gate swing (SS) of 0.12 V/decade, threshold voltage (VTH) of 0.5 V, and ION/OFF ratio of ∼109 even at the maximum processing temperature of 150 °C. Simultaneously, the optimized devices were resistant to exposure to external positive gate bias stress (PBS) and negative bias stress (NBS) for 3600 s, where the VTH shifts for exposure to PBS and NBS for this duration were 0.1 V and -0.15 V, respectively.

Schottky Gate Induced Threshold Voltage Instabilities in p-GaN Gate AlGaN/GaN HEMTs

We present detailed ON-state gate current characterization of Schottky gate p-GaN capped AlGaN/GaN high-electron-mobility transistors (HEMTs) on two distinct gate processes. The threshold voltage is monitored from 10 μs up to 100 s under positive gate bias stress and during recovery. The threshold voltage stability is affected by the balance between hole and electron current in the gate stack. More specifically, devices with uniform hole conduction across the p-GaN gate area demonstrate stable threshold voltage behavior up to V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g </sub> = 5 V, whereas devices with a dominating gate perimeter electron conduction demonstrate larger instabilities. Finally, the threshold voltage stability during OFF-state pulsed stress is investigated and correlated to the excess gate-to-drain charge extracted from capacitance curves.

Hydrogenated In–Ga–Zn–O thin-film transistors with anodized and fluorinated Al2O3 gate insulator for flexible devices

For the purpose of developing In–Ga–Zn–O (IGZO) thin-film transistors (TFTs) on a flexible substrate, low-temperature (150 °C) processed hydrogenated IGZO (IGZO:H) TFTs with anodize alumina gate insulator (Al2O3 GI) have been developed. We found that fluorination of the Al2O3 GI surface significantly improves field effect mobility (μ FE) and positive gate bias and temperature stress (PBTS) reliability of the TFTs. μ FE of 28.8 cm2 V−1 s−1 and good PBTS reliability were obtained from the IGZO:H TFTs with a 68 nm thick fluorinated Al2O3 GI. X-ray photoelectron spectroscopy analysis revealed that fluorine in the AlOF x formed at the Al2O3 surface played an important role in improving performance and PBTS reliability of low-temperature-processed oxide TFTs for future flexible device applications.

Ta2O5/SiO2 Multicomponent Dielectrics for Amorphous Oxide TFTs

Co-sputtering of SiO2 and high-κ Ta2O5 was used to make multicomponent gate dielectric stacks for In-Ga-Zn-O thin-film transistors (IGZO TFTs) under an overall low thermal budget (T = 150 °C). Characterization of the multicomponent layers and of the TFTs working characteristics (employing them) was performed in terms of static performance, reliability, and stability to understand the role of the incorporation of the high-κ material in the gate dielectric stack. It is shown that inherent disadvantages of the high-κ material, such as poorer interface properties and poor gate insulation, can be counterbalanced by inclusion of SiO2 both mixed with Ta2O5 and as thin interfacial layers. A stack comprising a (Ta2O5)x(SiO2)100 − x film with x = 69 and a thin SiO2 film at the interface with IGZO resulted in the best performing TFTs, with field-effect mobility (µFE) ≈ 16 cm2·V−1·s−1, subthreshold slope (SS) ≈ 0.15 V/dec and on/off ratio exceeding 107. Anomalous Vth shifts were observed during positive gate bias stress (PGBS), followed by very slow recoveries (time constant exceeding 8 × 105 s), and analysis of the stress and recovery processes for the different gate dielectric stacks showed that the relevant mechanism is not dominated by the interfaces but seems to be related to the migration of charged species in the dielectric. The incorporation of additional SiO2 layers into the gate dielectric stack is shown to effectively counterbalance this anomalous shift. This multilayered gate dielectric stack approach is in line with both the large area and the flexible electronics needs, yielding reliable devices with performance suitable for successful integration on new electronic applications.

Bias Stress Effects in Low Temperature Amorphous Hf-In-ZnO TFTs Using RF-sputtering HfO2 as High-k Gate Dielectric

In this work we analyze the electrical performance, contact resistance and the effects of positive and negative gatebias stress of Hf-In-ZnO/HfO2 thin film transistors. Devices were fabricated using RF-magnetron sputtering at room temperature and fully patterned, with operation voltage below 6 V. Devices with drain-currents up to 2x10-6 A and threshold voltages of ~2 V were analyzed under negative and positive gate bias stress. Devices under negative gate-bias stress showed a slightly threshold voltage shift due to the transistor channel is depleted of electrons at the channel/dielectric interface. Devices under positive gate-bias stress, showed threshold voltage shifts in the negative direction due to the reversible charge/discharge effect of the electrons in pre-existing high-k HfO2 bulk traps. Positive gate-bias stress does not cause any degeneration, since stressed devices tend to recover after 5 mins.

Gate Bias Stress Instability and Hysteresis Characteristics of InAs Nanowire Field-Effect Transistors.

Because of the excellent electrical properties, III-V semiconductor nanowires are promising building blocks for next-generation electronics; however, their rich surface states inevitably contribute large amounts of charge traps, leading to gate bias stress instability and hysteresis characteristics in nanowire field-effect transistors (FETs). Here, we investigated thoroughly the gate bias stress and hysteresis effects in InAs nanowire FETs. It is observed that the output current decreases together with the threshold voltage shifting to the positive direction when a positive gate bias stress is applied, and vice versa for the negative gate bias stress. For double-sweep transfer characteristics, the significant hysteresis behavior is observed, depending heavily on the sweeping rate and range. On the basis of complementary investigations of these devices, charge traps are confirmed to be the dominant factor for these instability effects. Importantly, the hysteresis can be simulated well by utilizing a combination of the rate equation for electron density and the empirical model for electron mobility. This provides an accurate evaluation of carrier mobility, which is in distinct contrast to the overestimation of mobility when using the transconductance for calculation. All these findings are important for understanding the charge trap dynamics to further enhance the device performance of nanowire FETs.

Surface Preconditioning and Postmetallization Anneal Improving Interface Properties and Vth Stability under Positive Gate Bias Stress in AlGaN/GaN MIS‐HEMTs

Trap states at the dielectric/GaN interface of AlGaN/GaN‐based metal–insulator–semiconductor high electron mobility transistors (MIS‐HEMTs) can cause threshold voltage (Vth) instability especially under positive gate bias stress. Herein, the influence of O2 plasma surface preconditioning (SPC) before the atomic layer deposition of the Al2O3 gate dielectric and of N2 postmetallization anneal (PMA) after gate metallization on the Al2O3/GaN interface quality is investigated. The interface is characterized by multifrequency capacitance–voltage measurements which show a smaller frequency dispersion after the employment of SPC and PMA treatments with a reduction of the interface trap density Dit to a value in the order of 2 × 1012 cm−2 eV−1 near the conduction band edge. The effectiveness of SPC and PMA is demonstrated in Al2O3/AlGaN/GaN MIS‐HEMTs by pulsed current–voltage measurements which reveal improved Vth stability.

Suppression of Edge Effect Induced by Positive Gate Bias Stress in Low-Temperature Polycrystalline Silicon TFTs With Channel Width Extension Over Source/Drain Regions

This study demonstrated that the edge effect induced by positive gate bias stress (PBS) was effectively eliminated by applying channel width extensions over source/drain regions in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). After PBS, a stress-induced hump current in subthreshold region is observed and is caused by the charge trapping into parasitic transistors along the channel width edges. This phenomenon is attributed to carrier injection occurring along the width edges since a high electric field is located at that region, where lots of defects are generated due to the definition of the active area during the etching process. In this study, we show that the degradation in electrical characteristics during the gate bias operation resulted from the edge effect can be eliminated when the TFT devices utilize the channel width extension in the active layer. Electrical measurements, numeral calculations, and a TCAD electrical simulation confirm that this geometry, which includes a channel extension along the width direction, can dramatically reduce the carrier injection at the edges even though high electric field is mainly located at the width edges during gate bias operation.

Various Reliability Investigations of Low Temperature Polycrystalline Silicon Tunnel Field-Effect Thin-Film Transistor

Various reliability issues of low temperature polycrystalline silicon (LTPS) tunnel field-effect transistor (TFET) are comprehensively studied for the first time and compared with conventional LTPS thin-film transistor (TFT). For the positive and negative gate bias stress (P/NGBS) instability, the NGBS causes more serious electrical degradation for both LTPS-TFETs and TFTs because of the higher trap state generation after the NGBS. However, the local P/NGBS near the source-side and drain-side regions show completely different impacts on the LTPS-TFETs and TFTs. The results reveal that the source-side local P/NGBS dominates the entire P/NGBS effects of LTPS-TFETs, and the drain-side local P/NGBS effects have less impacts on the electrical behavior of LTPS-TFETs compared with the entire P/NGBS effects. For the LTPS-TFTs, the local P/NGBS effects show much less electrical degradation than the entire P/NGBS. The difference of local P/NGBS effects between LTPS-TFETs and TFTs is attributed to the different carrier transport mechanisms. In addition to the P/NGBS effects, the hot carrier stress (HCS) with different drain stress voltages is also studied in this work. The drain stress voltage would introduce the horizontal electric field near the junction and reduce the impact of the vertical electric field in the channel region. For the HCS of LTPS-TFETs, the increase of drain stress voltage only leads to the reduction of vertical electric field stress effect but no horizontal electric field stress effect, which is different from the results of LTPS-TFT.

Hafnium Incorporation in InZnO Thin Film Transistors as a Carrier Suppressor.

In this study, we fabricated Hf-doped indium zinc oxide thin-film transistors (HIZO TFTs) using a solution process. Channel layers of the TFTs were optimized by varying the molar ratio of Hf in the channel layers. The electrical properties of the fabricated devices were compared to gallium indium zinc oxide (GIZO). HIZO TFTs showed 0.12 V threshold voltage, 0.45 V/decade subthreshold swing and 1.24 × 106 on-off current ratio, which were excellent compared to that of GIZO. In particular, when a positive gate bias stress of 10 V was applied for 10³ s, the HIZO TFT exhibited a lower threshold voltage shift of 1.11 V than the GIZO TFT (1.88 V). These results originate from the higher oxygen bonding with Hf in IZO compared to Ga atoms. We confirmed that Hf acts as an excellent carrier suppressor whose properties exceed those of Ga.