Various Reliability Investigations of Low Temperature Polycrystalline Silicon Tunnel Field-Effect Thin-Film Transistor

Abstract

Various reliability issues of low temperature polycrystalline silicon (LTPS) tunnel field-effect transistor (TFET) are comprehensively studied for the first time and compared with conventional LTPS thin-film transistor (TFT). For the positive and negative gate bias stress (P/NGBS) instability, the NGBS causes more serious electrical degradation for both LTPS-TFETs and TFTs because of the higher trap state generation after the NGBS. However, the local P/NGBS near the source-side and drain-side regions show completely different impacts on the LTPS-TFETs and TFTs. The results reveal that the source-side local P/NGBS dominates the entire P/NGBS effects of LTPS-TFETs, and the drain-side local P/NGBS effects have less impacts on the electrical behavior of LTPS-TFETs compared with the entire P/NGBS effects. For the LTPS-TFTs, the local P/NGBS effects show much less electrical degradation than the entire P/NGBS. The difference of local P/NGBS effects between LTPS-TFETs and TFTs is attributed to the different carrier transport mechanisms. In addition to the P/NGBS effects, the hot carrier stress (HCS) with different drain stress voltages is also studied in this work. The drain stress voltage would introduce the horizontal electric field near the junction and reduce the impact of the vertical electric field in the channel region. For the HCS of LTPS-TFETs, the increase of drain stress voltage only leads to the reduction of vertical electric field stress effect but no horizontal electric field stress effect, which is different from the results of LTPS-TFT.