PNP Bipolar Transistors Research Articles

Minimizing gain degradation in lateral PNP bipolar junction transistors using gate control

Gain degradation in lateral PNP bipolar junction transistors is minimized by controlling the potential of a gate terminal deposited above the active base region. Gate biases that deplete the base during radiation exposure establish electric fields in the base oxide that limit the generation of oxide defects. Conversely, gate biases that accumulate the base during device operation suppress gain degradation by decreasing the probability of carrier recombination with interface states. The results presented in this paper suggest that, for gate controlled LPNP transistors designed for operation in radiation environments, a dynamic control of the gate potential improves the transistor's radiation hardness and extend its operating life.

First epitaxial pnp bipolar transistoron diamond with deepnitrogen donor

Vertical pnp bipolar transistors on diamond have been fabricated by doping the base with deep nitrogen donor (E/sub c/-E/sub d/=1.7 eV). The pn junction formed by the nitrogen donors and boron acceptors was confirmed. Transistor characteristics in common emitter and common-base modes were measured at room temperature.

Total dose effects on gate controlled lateral PNP bipolar junction transistors

A gate controlled lateral PNP bipolar device has been designed in a commercial BiCMOS process to investigate its sensitivity to radiation-induced degradation. New experimental and simulated results concerning total dose effects are presented. The improved radiation hardness of this device working in its accumulation mode is shown. The influence of the gate potential during irradiation is studied as well as the effect of the gate potential on the degraded current characteristics.

An advanced PNP bipolar transistor design for a low-power and very-high-performance quarter-micron CBiCMOS process

This paper describes an advanced PNP bipolar transistor which has been designed by using the mixed two-dimensional device/circuit simulation (CODECS) [1] for a low-power and very-high-performance 0.25 μm complementary BiCMOS (CBiCMOS) device. The optimized PNP structure has a 30-nm-wide emitter, a 39-nm-wide intrinsic base region, a maximum cut-off frequency of 14 GHz and a current gain of 16 (without poly-Si emitter effect). A high performance and limits in terms of delay for pull-down of 0.25 μm CBiCMOS were obtained and compared to those offered by BiCMOS and complementary metal-oxide semiconductor circuits at different power supplies and charge capacitance. An improvement of 1.5 × at 1 pF, 1.6 × at 0.6 pF and 2 × at 0.2 pF over BiCMOS has been achieved.

Impact of geometrical scaling on parasitic pnp bipolar transistor in N-well, 0.25 μm CMOS devices and its effect on latchup immunity

This paper presents a detailed analysis of latchup dependence on geometrical dimensions of N-well, 0.25 μm complementary metal-oxide silicon (CMOS) devices with 50 Ågate oxide using simulation and experiment. Simulation results show that as dimensions continue to shrink, the traditionally accepted vertical parasitic pnp bipolar transistor becomes a lateral device. This observed result is very significant since increasing the N-well junction depth no longer guarantees improvement in latchup immunity. Experimental data shows that variation in p+ emitter to N-well edge spacing ( d plat) does not affect latchup characteristics as long as d plat is far greater than d pver, the difference between the N-well and p+ diffusion junction depth.

BiCMOS logic circuit for single-battery operation

A novel BiCMOS logic circuit is described that provides high-speed rail-to-rail operation with only one battery cell (1–1.5 V). The proposed circuit utilises a novel pull-down scheme that involves bootstrapping the base of the pull-down pnp bipolar junction transistor to a negative potential during the pull-down transient period. Circuit simulations have shown that the proposed circuit outperforms the transient-saturation full-swing BiCMOS and the bootstrapped bipolar CMOS circuits in terms of delay, power and cross-over capacitance for all simulated supply voltages.

The effect of emitter junction bias on the low dose-rate radiation response of bipolar devices

It is shown that emitter-base junction bias is significant for low dose rate irradiation response of npn and pnp bipolar transistors. The effect is more pronounced for pnp transistor. Experimental results are explained in terms of fringing electric field model. The role of fringing field is confirmed by the radiation induced charge neutralization experiment. The experimental results on the effect of emitter junction bias on the elevated temperature high dose rate irradiation of bipolar devices and its application for low dose rate response simulation are discussed.

Gain degradation of lateral and substrate pnp bipolar junction transistors

The effect of dose rate on radiation-induced current gain degradation at 20 krad(Si) was quantified for lateral and substrate pnp bipolar transistors over the range of 0.001 to 294 rad(Si)/s. Degradation increases monotonically with decreasing dose rate, such that, at an emitter-to-base voltage of 0.7 V, radiation-induced excess base current differs by a factor of approximately eight at the extreme dose rates. Degradation shows little dependence on dose rate below 0.005 rad(Si)/s, suggesting that further degradation enhancement at space-like dose rates may be negligible. In addition, the effect of ambient temperature on radiation-induced gain degradation at 294 rad(Si)/s was thoroughly investigated over the range of 25 to 240/spl deg/C. Degradation is enhanced with increasing temperature while simultaneously being moderated by in situ annealing such that, for a given total dose, an optimum irradiation temperature for maximum degradation results. Optimum irradiation temperature decreases logarithmically with total dose and is larger and more sensitive to dose in the substrate device than in the lateral device. Based on the measurement of midgap interface trap density in the base oxide, enhancement in transistor gain degradation due to elevated temperature is explained as an increase in surface recombination velocity in the base. Maximum high dose rate degradation at elevated temperature closely approaches low dose rate degradation for both devices. Based on high-temperature irradiations, a flexible procedure for the accelerated prediction of low dose rate gain degradation at 20 krad(Si) is developed for each of the devices studied.

Modeling ionizing radiation induced gain degradation of the lateral PNP bipolar junction transistor

Ionizing-radiation-induced gain degradation in lateral PNP bipolar junction transistors is due to an increase in base current as a result of recombination at the surface of the device. A qualitative model is presented which identifies the physical mechanism responsible for excess base current. The increase in surface recombination velocity due to interface traps results in an increase in excess base current and the positive oxide charge moderates the increase in excess base current and changes the slope of the current-voltage characteristics. Analytical and empirical models have been developed to quantitatively describe the excess base current response to ionizing radiation. It is shown that the surface recombination velocity dominates the excess base current response to total dose.

Unique dc characteristics of a new gated lateral pnp bipolar junction transistor (BJT) using 0.8 μm BiCMOS technology

In this paper, the detailed device dc performance of a gated lateral pnp (LPNP) device that has five terminals, collector C, base B, emitter E, gate G, and substrate S, and is fabricated in a 0.8 μm BiCMOS technology is described. Because this gated LPNP has two inputs and one output, it shows unique dc characteristics of variable current gain, βF, of 102 ~ 104 with VG variations of 0.4 to – 0.4 V; variable transconductance, gM, which increases 3 ~ 10 times as VE increases from 0.4 to 0.7 V. Based on these unique features, this new device is attractive for some analog circuit applications; for example, when used as a mixer, it has a conversion gain of 5–12 dB for an input RF signal up to 400 MHz.

Integrating Bipolar Junction Transistors with Silicon-Based Light-Emitting Devices

AbstractSilicon-based optoelectronic devices enable the realization of optoelectronic systems that are compatible with integrated circuit manufacturing technology. This work reports on silicon-based visible light-emitting devices (LEDs) that have been successfully integrated into a standard bipolar fabrication sequence. The basic LED structure consists of a 0.5–1.0μm thick silicon-rich silicon oxide (SRSO) active light-emitting layer formed on a p-type silicon wafer by partial oxidation of porous silicon (PSi), with an n+ doped polysilicon cathode. The LEDs exhibit bright electroluminescence (EL) with a spectral peak between 1.75 and 1.90e. The LEDs are connected in a common-emitter configuration to integrated vertical pnp bipolar driver transistors. This is the first demonstration of an all-silicon visible light emitter / bipolar transistor optoelectronic integrated circuit. The LED device fabrication, process integration, and optoelectronic device characteristics are discussed.

Trench-proximity effects on collector current in self-aligned NPN and PNP bipolar transistors

As lithographic ground rules are scaled into the deep sub-micron regime in today's VLSI technologies, the proximity of different materials in a given device structure often induces significant mechanical stress. In this paper, we report the observation of the collector current ( I c ) variation induced by the isolation trench in advanced bipolar devices. It is shown that as the trench-intrinsic device separation is pushed into deep sub-micron regime, I c decreases in the npn transistors, while it increases in the pnp transistors. We attribute the latter to an in-plane biaxial tensile stress which lowers the electron mobiity while enhances the hole mobility in the 〈001〉 (vertical) crystal orientation.

A fully complementary BiCMOS technology for 10 V mixed-signal circuit applications

A 10 V fully complementary BiCMOS technology, HBC-10, has been developed for high speed, low noise and high precision mixed signal system integration applications. In this technology, two varieties of CMOS transistors have been implemented for 10 V analog and 5 V digital applications. A gate oxide thickness of 30 nm is utilized for the 10 V CMOS transistors with a lightly doped drain extension added to the NMOS structure to achieve device lifetime in excess of 10 years. A gate oxide thickness of 18 nm is used for 5 V CMOS logic circuits. These transistors are specially architected so that they may also serve as analog transistors in 5 V circuit applications. The 5 V NMOS transistor lifetime is guaranteed by use of a double diffused drain structure. The active devices are isolated by a fully recessed 1.5 /spl mu/m oxide grown under high pressure conditions. Use of high pressure steam, plus combining diffusion operations where possible, results in a low overall thermal budget. This allows the up-diffusion of buried layers to be minimized so that a thin, 1.6 /spl mu/m epitaxial silicon layer is sufficient to support 10 V bipolar transistors. The resultant vertical PNP and NPN transistors are characterized with cut-off frequencies of more than 1.3 GHz and 5 GHz, respectively. Likewise, the associated products of the current gain and Early voltage of PNP and NPN bipolar transistors are more than 1000 and 6000 V, respectively. A precision, buried Zener diode (for voltage reference applications), PtSi Schottky diode, polysilicon-oxide-polysilicon capacitor and trimmable thin film resistor are integrated into this process. This wide variety of passive and active components is essential for system integration and has been carefully designed for precision analog applications. The total number of masking operations is 23, which includes double layer metallization.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Full-swing Schottky BiCMOS/BiNMOS and the effects of operating frequency and supply voltage scaling

Novel full-swing BiCMOS/BiNMOS logic circuits which use Schottky diode in the pull-up section for low supply-voltage regime are developed. The full-swing pull-up operation is performed by saturating the bipolar transistor with a base current pulse. After which, the base is isolated and bootstrapped to a voltage higher than V/sub DD/. The BiCMOS/BiNMOS circuits do not require a PNP bipolar transistor. They outperform other BiCMOS circuits at low supply voltage, particularly at 2 V using 0.5 /spl mu/m BiCMOS technology. Delay, area, and power dissipation comparisons have been performed. The new circuits offer delay reduction at 2 V supply voltage of 37% to 56% over CMOS. The minimum fanout at which the new circuits outperform CMOS gate is 2 to 3. Furthermore, the effect of the operating frequency on the delay of a wide range of BiCMOS and BiNMOS circuits is reported for the first time, showing the superiority of the Schottky circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An Investigation of the Inconsistency in Barrier Heights for PNP and NPN Polysilicon Emitter Bipolar Transistors Using a New Tunneling Model

A new tunneling model is proposed for polysilicon emitter bipolar transistors in which the interfacial layer is modeled as a wide band-gap semiconductor. This model predicts that potential barriers are formed in both the conduction and valence bands. The shapes and sizes of the barriers are dependent upon the amount of band-bending within the interfacial layer, which is in turn dependent on the amount of dopant segregation in the interfacial layer. Measurements of base current and emitter resistance are made on pnp polysilicon emitter bipolar transistors with deliberately grown interfacial oxide layers. These electrical characteristics are then modeled using the new heterojunction tunneling model, from which values of electron and hole barrier heights are extracted. Specifically, a hole barrier height of 0.31±0.02 eV is obtained, and an electron barrier height of either >0.68±0.08 eV or >0.44±0.06 eV, with the value depending on the band-gap narrowing model used in the calculation. These values of electron and hole barrier height are shown to be different than the values obtained when similar measurements are made on npn devices. The new heterojunction tunneling model is used to model these devices, and it is shown that it is capable of fully explaining this discrepancy between the values of barrier height obtained from measurements on npn and pnp transistors.

Hot-carrier effects in polysilicon emitter vertical PNP and NPN transistors

Hot-carrier effects due to reverse bias junctions of high performance vertical PNP bipolar transistors have been observed. Polysilicon emitter/base PNP devices both with and without deep trench isolation are examined. Comparisons are also made between high speed NPN and PNP transistors. The impact of a variety of stress conditions, BVebo, BVeco, BVceo and BVcbo has been studied.

Low-frequency noise correlations in lateral pnp bipolar transistors

Measurement results of low-frequency noise behaviour, and in particular, the noise correlations in lateral pnp bipolar transistors are presented for various bias conditions in both forward active and saturation regimes. The correlation in output collector noise is very high with a value close to unity only when the device is in medium injection. At extremely high injection, the degree of coherence degrades, depicting a behaviour similar to the forward current gain of the device. This degradation can be attributed to emitter-crowding effects. The correlation in output noise can be exploited to drastically suppress the intrinsic noise, particularly at low frequencies, making such devices useful for the input stage of amplifiers; the first step towards realisation of ultra low-noise amplifiers in standard integrated circuit technology.

Pnp resonant tunneling light emitting transistor

A pnp bipolar resonant tunneling transistor is realized using a base consisting of an n-type modulation doped quantum-well layer next to a double-barrier tunneling structure. Electrons are injected from the quantum-well base layer into the tunneling structure, leading to quantum-well light emission when they recombine with holes from the emitter. This optical output, which is modulated by the base voltage, persists in the negative differential resistance region of the current-voltage characteristics where the hole current is in oscillation. This opens possibilities for using this transistor as a high frequency electro-optical heterodyne convertor.

A Macintosh based transistor curve tracer and analyzer

A technique to easily and quickly obtain, display, and analyze the transistor characteristics of pnp and npn bipolar junction transistors with a Macintosh personal computer is reported. Both the necessary hardware and software are described.

High-gain lateral pnp bipolar transistors made using focused ion beam implantation

We report the fabrication of lateral pnp bipolar transistors using focused ion beam (FIB) implants of boron and phosphorus for the collector and base, respectively. The implants of B+, P+, and P++ were all at a dose of 1×1013 /cm2 and a beam voltage of 75 kV. These implants defined spaces between the emitter and collector regions of 0.5–1.50 μm; which, after diffusion and zero voltage depletion width effects were considered, produced effective on‐wafer device basewidths of ∼0.2 μm. For the best devices, values of hFE near 100 were obtained with good junction characteristics and at peak collector currents of 10 μA/μm of device width.