Impact of geometrical scaling on parasitic pnp bipolar transistor in N-well, 0.25 μm CMOS devices and its effect on latchup immunity

Abstract

This paper presents a detailed analysis of latchup dependence on geometrical dimensions of N-well, 0.25 μm complementary metal-oxide silicon (CMOS) devices with 50 Ågate oxide using simulation and experiment. Simulation results show that as dimensions continue to shrink, the traditionally accepted vertical parasitic pnp bipolar transistor becomes a lateral device. This observed result is very significant since increasing the N-well junction depth no longer guarantees improvement in latchup immunity. Experimental data shows that variation in p+ emitter to N-well edge spacing ( d plat) does not affect latchup characteristics as long as d plat is far greater than d pver, the difference between the N-well and p+ diffusion junction depth.