Abstract
A new circuit model for a four t erminal VDMOSFET fabricated in a junction isolated smart power technology is proposed. The model equations are d erived from fundamental device physics to describe the MOS channel, the voltage dependent drift region resistance and the gate-drain capacitance. The substrate current is calculated from a parasitic PNP bipolar transistor. The advantage of the coupling between the DC and AC characteristics with respect to clear parameter extraction is demonstrated.
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