Pipelined Hardware Architecture Research Articles

Parallelized RDOQ Algorithm and Fully Pipelined Hardware Architecture for AVS3 Video Coding

Parallelized RDOQ Algorithm and Fully Pipelined Hardware Architecture for AVS3 Video Coding

Adaptive Pipeline Hardware Architecture Design and Implementation for Image Lossless Compression/Decompression Based on JPEG-LS

Adaptive Pipeline Hardware Architecture Design and Implementation for Image Lossless Compression/Decompression Based on JPEG-LS

Fast Linear Equation Solving Algorithm and its Pipelined Hardware Architecture Design for VVC Affine Motion Estimation

Fast Linear Equation Solving Algorithm and its Pipelined Hardware Architecture Design for VVC Affine Motion Estimation

Pipelined Key Switching Accelerator Architecture for CKKS-Based Fully Homomorphic Encryption

The increasing ubiquity of big data and cloud-based computing has led to increased concerns regarding the privacy and security of user data. In response, fully homomorphic encryption (FHE) was developed to address this issue by enabling arbitrary computation on encrypted data without decryption. However, the high computational costs of homomorphic evaluations restrict the practical application of FHE schemes. To tackle these computational and memory challenges, a variety of optimization approaches and acceleration efforts are actively being pursued. This paper introduces the KeySwitch module, a highly efficient and extensively pipelined hardware architecture designed to accelerate the costly key switching operation in homomorphic computations. Built on top of an area-efficient number-theoretic transform design, the KeySwitch module exploited the inherent parallelism of key switching operation and incorporated three main optimizations: fine-grained pipelining, on-chip resource usage, and high-throughput implementation. An evaluation on the Xilinx U250 FPGA platform demonstrated a 1.6× improvement in data throughput compared to previous work with more efficient hardware resource utilization. This work contributes to the development of advanced hardware accelerators for privacy-preserving computations and promoting the adoption of FHE in practical applications with enhanced efficiency.

Hardware Architecture for Realtime HEVC Intra Prediction

Researchers have, in recent times, achieved excellent compression efficiency by implementing a more complicated compression algorithm due to the rapid development of video compression. As a result, the next model of video compression, High-Efficiency Video Coding (HEVC), provides high-quality video output while requiring less bandwidth. However, implementing the intra-prediction technique in HEVC requires significant processing complexity. This research provides a completely pipelined hardware architecture solution capable of real-time compression to minimize computing complexity. All prediction unit sizes of 4×4, 8×8, 16×16, and 32×32, and all planar, angular, and DC modes are supported by the proposed solution. The synthesis results mapped to Xilinx Virtex 7 reveal that our solution can do real-time output with 210 frames per second (FPS) at 1920×1080 resolution, called Full High Definition (FHD), or 52 FPS at 3840×2160 resolution, called 4K, while operating at 232 Mhz maximum frequency.

List-serial pipelined hardware architecture for SCL decoding of polar codes

For polar codes, the performance of successive cancellation list (SCL) decoding is capable of approaching that of maximum likelihood decoding. However, the existing hardware architectures for the SCL decoding suffer from high hardware complexity due to calculating L decoding paths simultaneously, which are unfriendly to the devices with limited logical resources, such as field programmable gate arrays (FPGAs). In this paper, we propose a list-serial pipelined hardware architecture with low complexity for the SCL decoding, where the serial calculation and the pipelined operation are elegantly combined to strike a balance between the complexity and the latency. Moreover, we employ only one successive cancellation (SC) decoder core without L×L crossbars, and reduce the number of inputs of the metric sorter from 2L to L + 2. Finally, the FPGA implementations show that the hardware resource consumption is significantly reduced with negligible decoding performance loss.

Low Complexity Implementation of OTFS Transmitter using Fully Parallel and Pipelined Hardware Architecture

Low Complexity Implementation of OTFS Transmitter using Fully Parallel and Pipelined Hardware Architecture

Real-Time Fast Channel Clustering for LiDAR Point Cloud

LiDAR sensors can produce point clouds with precise 3D depth information that is essential for autonomous vehicles and robotic systems. As a perception task, point cloud clustering algorithms can be applied to segment the points into object instances. In this brief, we propose a novel, hardware-friendly fast channel clustering (FCC) algorithm that achieves state-of-the-art performance when evaluated using KITTI panoptic segmentation benchmark. Furthermore, an efficient, pipeline hardware architecture is proposed to implement the FCC algorithm on an FPGA. Experiments show that the hardware design can process each LiDAR frame with 64 channels, 2048 horizontal resolution at various point sparsity in 1.93 ms, which is more than 471.5 times faster than running on the CPU. The code will be released to the public via GitHub.

On-Orbit Real-Time Variational Image Destriping: FPGA Architecture and Implementation

On-orbit real-time image processing is of increasing demands due to requirements for quick-response missions. Image destriping is usually an important pre-processing step to improve image quality in practice. The unidirectional variational models have shown impressive destriping performance. However, they are not easy for real-time implementation for high-computation complexity and there are few attempts for hardware implementation. This article is the first hardware implementation of variational image destriping algorithm, which achieves high throughput for large-swath remote-sensing images. In this article, a fully pipelined hardware architecture is proposed. First, the involved iteration loop is unrolled and a coarse-grained parallelism is obtained. Second, for each deployed iteration computation blocks (ICBs), a dedicated timing arrangement is designed to alleviate the bottleneck caused by the data dependency within each ICB, obtaining a fine-grained parallelism. Moreover, to further optimize the critical path, an approximate simplification scheme is proposed, saving the resource usage and reducing computing delay. The proposed architecture is implemented and verified on a XILINX 6vcx240t field programmable gate array (FPGA); it achieves a maximum frame rate up to 41.9 frames/s with delay of only tens of row cycles for 8-bit <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${{2048}} \times {{2048}}$ </tex-math></inline-formula> images. It performs all the processing on the pixels in raster scan order on- the-fly as they are being transmitted from camera payload, which significantly facilitates on- orbit real-time processing of large-swath remote-sensing images with high data rate.

Scalable Fully Pipelined Hardware Architecture for In-Network Aggregated AllReduce Communication

The Ring-AllReduce framework is currently the most popular solution to deploy industry-level distributed machine learning tasks. However, only about half of the maximum bandwidth can be achieved in the optimal condition. In recent years, several in-network aggregation frameworks have been proposed to overcome the drawback, but limited hardware information have been disclosed. In this paper, we propose a scalable fully-pipelined architecture that handles tasks like forwarding, aggregation and retransmission with no bandwidth loss. The architecture is implemented on a Xilinx Ultrascale FPGA that connects to 8 working servers with 10 Gb/s network adapters, and it is able to scale to more complicated scenarios involving more workers. Compared with Ring-AllReduce, using AllReduce-Switch improves the efficient bandwidth of AllReduce communication with a ratio of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.75\times $ </tex-math></inline-formula> . In image training tasks, the proposed hardware architecture helps to achieve up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.67\times $ </tex-math></inline-formula> speedup to the training process. For computing-intensive models, the speedup from communication may be partially hidden by computing. In particular, for ResNet-50, AllReduce-Switch improves the training process with MPI and NCCL by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.30\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.04\times $ </tex-math></inline-formula> respectively.

Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES.

Currently, cryptographic algorithms are widely applied to communications systems to guarantee data security. For instance, in an emerging automotive environment where connectivity is a core part of autonomous and connected cars, it is essential to guarantee secure communications both inside and outside the vehicle. The AES algorithm has been widely applied to protect communications in onboard networks and outside the vehicle. Hardware implementations use techniques such as iterative, parallel, unrolled, and pipeline architectures. Nevertheless, the use of AES does not guarantee secure communication, because previous works have proved that implementations of secret key cryptosystems, such as AES, in hardware are sensitive to differential fault analysis. Moreover, it has been demonstrated that even a single fault during encryption or decryption could cause a large number of errors in encrypted or decrypted data. Although techniques such as iterative and parallel architectures have been explored for fault detection to protect AES encryption and decryption, it is necessary to explore other techniques such as pipelining. Furthermore, balancing a high throughput, reducing low power consumption, and using fewer hardware resources in the pipeline design are great challenges, and they are more difficult when considering fault detection and correction. In this research, we propose a novel hybrid pipeline hardware architecture focusing on error and fault detection for the AES cryptographic algorithm. The architecture is hybrid because it combines hardware and time redundancy through a pipeline structure, analyzing and balancing the critical path and distributing the processing elements within each stage. The main contribution is to present a pipeline structure for ciphering five times on the same data blocks, implementing a voting module to verify when an error occurs or when output has correct cipher data, optimizing the process, and using a decision tree to reduce the complexity of all combinations required for evaluating. The architecture is analyzed and implemented on several FPGA technologies, and it reports a throughput of 0.479 Gbps and an efficiency of 0.336 Mbps/LUT when a Virtex-7 is used.

A Resource-Efficient Pipelined Architecture for Real-Time Semi-Global Stereo Matching

It is still a grand challenge to implement a high-accuracy and high-performance stereo matching algorithm on a resource-limited hardware platform in stereo vision systems. This paper proposes a resource-efficient pipelined hardware architecture with four-cycle time-sharing for the semi-global matching (SGM) algorithm with weighted path cost aggregation. To save hardware resources, we also combined image down-sampling and disparity skipping in the SGM algorithm. The presented architecture is synthesized and implemented on a Zynq-7 FPGA board, which results in a throughput of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${1280 \times 960/62.5}$ </tex-math></inline-formula> fps with 75 disparity levels at the maximum frequency of 216 MHz. To improve the accuracy of the disparity map at close range, we also adapt the presented architecture with two-cycle time-sharing, and the disparity range is increased to 128, which attains the processing of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${1280 \times 960/116}$ </tex-math></inline-formula> fps at 200 MHz on VCU-118 FPGA board; the throughput reaches 18245 MDE/s. The result shows that the whole architecture only takes 50465 LUTs, 48046 Registers, 125.5 BRAMs with 128 disparity levels, which is much more efficient than the latest reference work.

Optimizing MRI Registration using Software/Hardware Co-Design Model on FPGA

The correct localization of brain tissue deformation and determination of the tumor growth relies majorly on the accuracy of the process known by image registration. Poor registration may lead to misclassified diseases and highly affect image-guided surgery and radiation therapies. Voxel-based morphometry (VBM) is an image analytical technique encompassing accurate registration but suffers from intensive time computations, similar to most of image registration techniques. Achieving the compromise between accuracy and computations is a challenging mission. Field programmable gate arrays have fast-evolving and customizable hardware acceleration capabilities that promise to help speed up computational tasks. This paper presents a software/hardware co-design model for accelerating the implementation of the diffeomorphic image registration algorithm ‘DARTEL’ as a part of VBM that analyzes MRI images. An optimized and pipelined hardware architecture is proposed and integrated into the Statistical Parametric Mapping (SPM) software tool that runs the DARTEL. Acceleration of the DARTEL registration algorithm resulted in a speedup factor of 114x on function-level, compared to the CPU with a contribution of 8x faster for the overall performance in the registration process of the SPM. The proposed model is successfully validated for the identification of Alzheimer’s disease based on T1-weighted MRI. A proposed software/hardware co-design model for VBM achieves remarkable acceleration while maintaining classification accuracy and proving proficiency against other CPU and GPU implementations.

Hardware Prototyping and Modelling of Prototype Filter for FBMC

Filter bank multicarrier (FBMC) is one of the effective candidates for the fifth generation of wireless communication networks. 5G (5th-generation wireless systems) is accepted as the next major stage of mobile telecommunication technology. The extent of 5G will be expanded mobile broadband services to next-generation automobiles and connected machines. In particular, filter bank multicarrier with offset quadrature amplitude modulation (FBMC/OQAM) is determined as the future generation 5G air interface by researchers recently. Filter bank multicarrier (FBMC) is admitted as one of the alternative technologies for multicarrier modulation. Compared to orthogonal frequency-division multiplexing (OFDM), FBMC has better spectrum shape and supports mobility. Therefore, efficient hardware implementations have highly interested researchers. Cyclic prefix (CP) and guard band are used for orthogonal frequency-division multiplexing (OFDM) and this causes loss of spectral efficiency, but FBMC applications do not need CP and guard band. Due to the fact that FBMC has offset QAM (OQAM) and band-limited filtering features on each subcarrier, the need for CP and guard band is eliminated. In this paper, novel pipelined hardware architecture of the filter design of FBMC/OQAM modulator has been proposed.

Design and VLSI Implementation of a Reduced-Complexity Sorted QR Decomposition for High-Speed MIMO Systems

In this article, a low-complexity and high-throughput sorted QR decomposition (SQRD) for multiple-input multiple-output (MIMO) detectors is presented. To reduce the heavy hardware overhead of SQRD, we propose an efficient SQRD algorithm based on a novel modified real-value decomposition (RVD). Compared to the latest study, the proposed SQRD algorithm can save the computational complexity by more than 44.7% with similar bit error rate (BER) performance. Furthermore, a corresponding deeply pipelined hardware architecture implemented with the coordinate rotation digital computer (CORDIC)-based Givens rotation (GR) is designed. In the design, we propose a time-sharing Givens rotation structure utilizing CORDIC modules in idle state to share the concurrent GR operations of other CORDIC modules, which can further reduce hardware complexity and improve hardware efficiency. The proposed SQRD processor is implemented in SMIC 55-nm CMOS technology, which processes 62.5 M SQRD per second at a 250-MHz operating frequency with only 176.5 kilo-gates. Compared to related studies, the proposed design has the best normalized hardware efficiency and achieves a 6-Gbps MIMO data rate which can support current high-speed wireless communication systems such as IEEE 802.11ax.

Hardware chip performance analysis of different FFT architecture

ABSTRACT The Fast Fourier Transform (FFT) is one of the most important algorithm used in digital signal processing (DSP) and digital communication applications to compute fast operations. FFT and IFFT is widely used in modulation and demodulation schemes such as Orthogonal Frequency Division Multiplexing (OFDM), TV broadcasting (DVD), Digital radio broadcasting (DVB) etc. The different FFT processor architectures are used for several applications. The Xilinx ISE tool has FFT Core, which can be directly used for several applications. FFT support four types of architectures: Radix-2 lite burst I/O, Radix-2 burst I/O, Radix-4 burst I/O and Pipelined I/O. The research article focuses on the hardware chip performance analysis of the variable length FFT processor architectures on Field Programmable Gate Array (FPGA) platform using VHDL programming in which FFT length varies from 8 point to 65,536 point. The input data stream is considered of 8-bit, 16-bit and 32-bit. The estimated hardware chip performance parameters are DSP Slices and block RAM. The timing parameter are transform cycles and frequency. It is estimated that radix-2 lite burst I/O performs better in terms of hardware resource utilisation on FPGA and pipelined hardware architecture performs better in terms of transform cycles in comparison to other FFT architectures. The decoded 1024-point FFT signal is observed in Xilinx ISE software integrated Chipscope Pro-Analyzer. The analysis predicts about the best-suited FFT hardware architecture when the designer is going to design the hardware chip on FPGA platform for several applications.

Efficient Successive Over Relaxation Detectors for Massive MIMO

Massive multiple-input and multiple-output (MIMO) is considered as an advanced technique in wireless communication due to its high spectral efficiency, data rates, and transmission reliability. However, the large number of antennas makes it challenging to design efficient detectors since computational complexity is much higher. Thus, conventional linear methods like minimum mean square error (MMSE) detection suffer from prohibitive complexity. To balance complexity and performance, a class of iterative linear methods are considered to approach MMSE performance with $\mathcal {O}({N_{T}}^{2})$ complexity, where $N_{T}$ is the number of transmit antennas. Among them, successive over relaxation (SOR) detector is promising since it achieves near MMSE performance with affordable complexity and fast convergence. However, error performance of previously proposed SOR detectors is sensitive to a relaxation factor $\omega $ , especially when the channel varies. To address this issue, two detectors are proposed in this paper: non-adaptive SOR (NA-SOR) detector (with fixed $\omega $ ) and adaptive SOR (A-SOR) detector (with iteratively changed $\omega $ ). Compared to prior SOR detectors, the performance of the NA-SOR detector is more robust to $\omega $ , and the A-SOR detector achieves better performance, especially in highly correlated channels. An efficient pipelined hardware architecture of the A-SOR detector is proposed. Implementation results show advantages when compared to the state-of-the-art (SOA).

A Pipelined Reduced Complexity Two-Stages Parallel LMS Structure for Adaptive Beamforming

In this paper, we propose a reduced complexity parallel least mean square structure (RC-pLMS) for adaptive beamforming and its pipelined hardware implementation. RC-pLMS is formed by two least mean square (LMS) stages operating in parallel (pLMS), where the overall error signal is derived as a combination of individual stage errors. The pLMS is further simplified to remove the second independent set of weights resulting in a reduced complexity pLMS (RC-pLMS) design. In order to obtain a pipelined hardware architecture of our proposed RC-pLMS algorithm, we applied the delay and sum relaxation technique (DRC-pLMS). Convergence, stability and quantization effect analysis are performed to determine the upper bound of the step size and assess the behavior of the system. Computer simulations demonstrate the outstanding performance of the proposed RC-pLMS in providing accelerated convergence and reduced error floor while preserving a LMS identical $O(N)$ complexity, for an antenna array of $N$ elements. Synthesis and implementation results show that the proposed design achieves a significant increase in the maximum operating frequency over other variants with minimal resource usage. Additionally, the resulting beam radiation pattern show that the finite precision DRC-pLMS implementation presents similar behavior of the infinite precision theoretical results.

A fast approach for bitcoin blockchain cryptocurrency mining system

The growth of the blockchain-based cryptocurrencies has attracted a lot of attention from a variety of fields, especially in academic research. One of them is Bitcoin, the most popular and highest valued cryptocurrency on the market. The SHA256 is the main processing part in Bitcoin mining, to date the difficulty of which is extremely high and still increases relentlessly. Hence, it is essential to improve the speed of the SHA256 cores in the Bitcoin mining system. In this paper, we propose a two-level pipeline hardware architecture for the SHA256 processing. The first-level pipeline helps the system reduce the number of operating cycles. Besides, the maximum frequency of the system is boosted by the second-level pipeline. The proposed hardware is implemented on FPGA Xilinx Virtex 7-VC707 (28 nm technology). The mining hash rate using the proposed pipeline SHA256 cores reaches 514.92 MH/s that improves 2.4 times compared to the FPGA based conventional technique. The throughput of SHA core of current study is 296.108 Gbps that is 240 times higher compared to the standard technique. The proposed architecture is also implemented in an ASIC design using ROHM 180 nm CMOS technology, which resulted in a throughput of 69.28 Gbps that is 18 times higher than that of conventional work implemented in Intel 14 nm process.

Efficient MIMO Preprocessor With Sorting-Relaxed QR Decomposition and Modified Greedy LLL Algorithm

This paper proposes a high-efficient preprocessing algorithm for $16\times 16$ MIMO detections. The proposed algorithm combines a sorting-relaxed QR decomposition (SRQRD) and a modified greedy LLL (MGLLL) algorithm. First, SRQRD is conducted to decompose the channel matrices. This decomposition adopts a relaxed sorting strategy together with a paralleled Givens Rotation (GR) array scheme, which can reduce the processing latency by 60% compared with conventional sorted QR decomposition (SQRD). Then, an MGLLL algorithm is conducted to improve detection performance further. The MGLLL algorithm adopts a paralleled selection criterion, and only process the most urgent iterations. Thus the processing latency and column swaps can be reduced by 50% and 75%, respectively, compared with the standard LLL algorithm. Finally, the bit-error-rate (BER) performance of this preprocessing algorithm is evaluated using two MIMO detectors. Results indicate that this preprocessor suffers a negligible performance degradation compared with the combination of the standard LLL algorithm and SQRD. Based on this preprocessing algorithm, a pipelined hardware architecture is also designed in this paper. A series of systolic coordinated-rotation-digital-computer (CORDIC) arrays are utilized, and highly-pipelined circuits are designed, helping this architecture achieve high frequency performance. This architecture is implemented using 65-nm CMOS technology, which can work at a maximum frequency of 625 MHz to process channel matrices every 16 clock cycles. The latency is 0.9 us. Comparisons indicate that this preprocessor outperforms other similar designs in terms of latency, throughput, and gate-efficiency.