Hardware chip performance analysis of different FFT architecture

Abstract

ABSTRACT The Fast Fourier Transform (FFT) is one of the most important algorithm used in digital signal processing (DSP) and digital communication applications to compute fast operations. FFT and IFFT is widely used in modulation and demodulation schemes such as Orthogonal Frequency Division Multiplexing (OFDM), TV broadcasting (DVD), Digital radio broadcasting (DVB) etc. The different FFT processor architectures are used for several applications. The Xilinx ISE tool has FFT Core, which can be directly used for several applications. FFT support four types of architectures: Radix-2 lite burst I/O, Radix-2 burst I/O, Radix-4 burst I/O and Pipelined I/O. The research article focuses on the hardware chip performance analysis of the variable length FFT processor architectures on Field Programmable Gate Array (FPGA) platform using VHDL programming in which FFT length varies from 8 point to 65,536 point. The input data stream is considered of 8-bit, 16-bit and 32-bit. The estimated hardware chip performance parameters are DSP Slices and block RAM. The timing parameter are transform cycles and frequency. It is estimated that radix-2 lite burst I/O performs better in terms of hardware resource utilisation on FPGA and pipelined hardware architecture performs better in terms of transform cycles in comparison to other FFT architectures. The decoded 1024-point FFT signal is observed in Xilinx ISE software integrated Chipscope Pro-Analyzer. The analysis predicts about the best-suited FFT hardware architecture when the designer is going to design the hardware chip on FPGA platform for several applications.