Efficient MIMO Preprocessor With Sorting-Relaxed QR Decomposition and Modified Greedy LLL Algorithm

Lirui Chen,Shikai Qiu,Yongzhong Li,Zuocheng Xing

doi:10.1109/access.2020.2980922

Abstract

This paper proposes a high-efficient preprocessing algorithm for $16\times 16$ MIMO detections. The proposed algorithm combines a sorting-relaxed QR decomposition (SRQRD) and a modified greedy LLL (MGLLL) algorithm. First, SRQRD is conducted to decompose the channel matrices. This decomposition adopts a relaxed sorting strategy together with a paralleled Givens Rotation (GR) array scheme, which can reduce the processing latency by 60% compared with conventional sorted QR decomposition (SQRD). Then, an MGLLL algorithm is conducted to improve detection performance further. The MGLLL algorithm adopts a paralleled selection criterion, and only process the most urgent iterations. Thus the processing latency and column swaps can be reduced by 50% and 75%, respectively, compared with the standard LLL algorithm. Finally, the bit-error-rate (BER) performance of this preprocessing algorithm is evaluated using two MIMO detectors. Results indicate that this preprocessor suffers a negligible performance degradation compared with the combination of the standard LLL algorithm and SQRD. Based on this preprocessing algorithm, a pipelined hardware architecture is also designed in this paper. A series of systolic coordinated-rotation-digital-computer (CORDIC) arrays are utilized, and highly-pipelined circuits are designed, helping this architecture achieve high frequency performance. This architecture is implemented using 65-nm CMOS technology, which can work at a maximum frequency of 625 MHz to process channel matrices every 16 clock cycles. The latency is 0.9 us. Comparisons indicate that this preprocessor outperforms other similar designs in terms of latency, throughput, and gate-efficiency.

Highlights

Multiple-input-multiple-output (MIMO) technique has been extensively utilized in wireless communications to increase spectrum efficiency [1]
In the proposed sorting-relaxed QR decomposition (SRQRD) algorithm, as presented on lines 11-12 of Algorithm 2, k columns with the minimum norm values are selected at one time, so the nullifying procedures for these columns can be performed in parallel
The above simulations are conducted using the K-best MIMO detector, which indicates that the proposed preprocessing algorithm can significantly improve the detection performance; and that the proposed SRQRD and modified greedy LLL (MGLLL) algorithms suffer from negligible performance degradation while reducing latency and complexity compared with other conventional sorted QR decomposition (SQRD) and non-greedy LLL algorithms

Summary

INTRODUCTION

Multiple-input-multiple-output (MIMO) technique has been extensively utilized in wireless communications to increase spectrum efficiency [1]. Conventional implementations [22], [23] about the LLL algorithm consider the worst case that each iteration of the LLL algorithm would perform the column swap procedure, which leads to low hardware utilization because no calculation is required for some iterations according to the condition-check results. In the proposed SRQRD algorithm, as presented on lines 11-12 of Algorithm 2, k columns with the minimum norm values are selected at one time, so the nullifying procedures for these columns can be performed in parallel (as detailed below). As shown in Fig., level-1 parallelism exists within the same column that the matrix entries are processed concurrently, whereas the conventional GR-based SQRD algorithm uses rii to nullify ri+1:N,i one by one. The proposed SRQRD algorithm is promising to reduce the latency by approximately 65% compared with conventional SQRD

MODIFIED GREEDY LLL ALGORITHM

HARDWARE ARCHITECTURE

IMPLEMENTATION RESULTS AND COMPARISONS

CONCLUSION