List-serial pipelined hardware architecture for SCL decoding of polar codes

Abstract

For polar codes, the performance of successive cancellation list (SCL) decoding is capable of approaching that of maximum likelihood decoding. However, the existing hardware architectures for the SCL decoding suffer from high hardware complexity due to calculating L decoding paths simultaneously, which are unfriendly to the devices with limited logical resources, such as field programmable gate arrays (FPGAs). In this paper, we propose a list-serial pipelined hardware architecture with low complexity for the SCL decoding, where the serial calculation and the pipelined operation are elegantly combined to strike a balance between the complexity and the latency. Moreover, we employ only one successive cancellation (SC) decoder core without L×L crossbars, and reduce the number of inputs of the metric sorter from 2L to L + 2. Finally, the FPGA implementations show that the hardware resource consumption is significantly reduced with negligible decoding performance loss.