Partially-depleted SOI Research Articles

Design and Study of a Novel P-Type Junctionless FET for High Performance of CMOS Inverter.

In this paper, a novel p-type junctionless field effect transistor (PJLFET) based on a partially depleted silicon-on-insulator (PD-SOI) is proposed and investigated. The novel PJLFET integrates a buried N+-doped layer under the channel to enable the device to be turned off, leading to a special work mechanism and optimized performance. Simulation results show that the proposed PJLFET demonstrates an Ion/Ioff ratio of more than seven orders of magnitude, with Ion reaching up to 2.56 × 10-4 A/μm, Ioff as low as 3.99 × 10-12 A/μm, and a threshold voltage reduced to -0.43 V, exhibiting excellent electrical characteristics. Furthermore, a new CMOS inverter comprising a proposed PJLFET and a conventional NMOSFET is designed. With the identical geometric dimensions and gate electrode, the pull-up and pull-down driving capabilities of the proposed CMOS are equivalent, showing the potential for application in high-performance chips in the future.

In vestigation the Impact of Silicon Film Thickness on FDSOI and PDSOI MOSFET Characteristics

The performance of chip is degraded because of the short-channel effect (SCE) as the metal oxide semiconductor field effect transistor (MOSFET) size scales down. Silicon on insulator (SOI) technology helps to reduce the short channel effects and permits a good solution to the miniaturization. The electrical characteristics of fully depleted SOI (FDSOI) and partially depleted SOI (PDSOI) n-channel MOSFET (N-MOSFET) are investigated as silicon film thickness is varied in this paper. Both transistors are compared in terms of electrical parameters which are the threshold voltage, subthreshold slope, on-state current, leakage current and drain induced barrier lowering (DIBL). Silvaco TCAD tools are used for simulating both PDSOI and FDSOI MOSFETs. FDSOI MOSFET is superior to PDSOI MOSFET based on found simulation results.

Experimental Study on Critical Parameters Degradation of Nano PDSOI MOSFET under TDDB Stress.

In today's digital circuits, Si-based MOS devices have become the most widely used technology in medical, military, aerospace, and aviation due to their advantages of mature technology, high performance, and low cost. With the continuous integration of transistors, the characteristic size of MOSFETs is shrinking. Time-dependent dielectric electrical breakdown (TDDB) is still a key reliability problem of MOSFETs in recent years. Many researchers focus on the TDDB life of advanced devices and the mechanism of oxide damage, ignoring the impact of the TDDB effect on device parameters. Therefore, in this paper, the critical parameters of partially depleted silicon-on-insulator (PDSOI) under time-dependent dielectric electrical breakdown (TDDB) stress are studied. By applying the TDDB acceleration stress experiment, we obtained the degradation of the devices' critical parameters including transfer characteristic curves, threshold voltage, off-state leakage current, and the TDDB lifetime. The results show that TDDB acceleration stress will lead to the accumulation of negative charge in the gate oxide. The negative charge affects the electric field distribution. The transfer curves of the devices are positively shifted, as is the threshold voltage. Comparing the experimental data of I/O and Core devices, we can conclude that the ultra-thin gate oxide device's electrical characteristics are barely affected by the TDDB stress, while the opposite is true for a thick-gate oxide device.

An Analytical Model for Weak Avalanche Induced Kink Effect of PDSOI nMOSFETs

Silicon-on-insulator (SOI) devices and circuits are widely used in semiconductor industry for its superior natures on integration density, isolations degree. Inefficient body contact of partially-depleted SOI (PDSOI) devices cannot evacuate excess carriers which transported from the weak avalanche multiplication of pinch-off region at high drain voltage bias. These accumulated carriers elevate the internal body potential and trigger electrical effects namely the body bias effect of threshold voltage and the turn-on of parasitic bipolar junction transistor (BJT). A comprehensive analytical model which include all these mechanisms are proposed to describe this kink effect. This model is constructed by an equivalent circuit and five strong nonlinearly coupled equations to describe the electrical behaviors. To solve these equations, a C <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$++$</tex-math> </inline-formula> Qt-based graphical interface software is developed for the parameter extraction of the model. The fixed point iteration algorithm are adopted for the solution of equations. The effectiveness and accuracy of this model are verified by the T-gate shaped PDSOI nMOSFETs of 130 nm manufacturing process node. It can predict the electrical behaviors of kink effect. This is meaningful for the circuit simulation of PDSOI platform.

Investigation of Temperature Dependence of mmWave Power Amplifier Large-Signal Reliability Performance

This work aims to study the temperature dependence on the long-term reliability of a power amplifier (PA) cell fabricated using 40-nm partially depleted-silicon on insulator (PD-SOI) nFET under dc and large-signal RF stress. Voltage swing caused by large RF signals complicates the stress mechanism due to frequent switching of stress from conducting to nonconducting. The impact of temperature on the time slope exponent ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${n}$ </tex-math></inline-formula> ) is also analyzed to understand the degradation mechanism at different temperatures. The values of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${n}$ </tex-math></inline-formula> are found to increase with the temperature pointing to the generation of new defects at the interface. A comparative reliability analysis is presented for dc, small-, and large-signal performance under varied accelerated dc and large-signal stress at drain and gate for different temperatures. Unity gain frequencies are also temperature sensitive and show high degradation at elevated temperatures. In our study, we have investigated the lifetime as a function of temperature of the PA operating in compression. It is observed that the lifetime is more than ten years when the PA operates at room temperature, which deteriorates as the measurement chuck temperature rises.

Area-efficient radiation-hardened 6 T SOI SRAM cell design using TDBC Transistors

Single event upset (SEU) is a critical issue for the static random access memory (SRAM) exposed to irradiated environments. In this paper, an area-efficient 6 T SRAM cell design based on partially depleted silicon-on-insulator (PDSOI) technology is proposed to improve the ability to resist SEU using tunnel-diode body-contact (TDBC) transistors. The proposed cell and 6 T floating body (FB) SOI SRAM cell are fabricated using 130 nm PDSOI technology for comparison purposes. Pulsed laser experiments show that, at the nominal supply voltage of 1.2 V, the energy threshold of the proposed cell increases by 25.2 % compared to the 6 T FB SOI cell with a similar area. The energy threshold of the traditional T-gate body-contact (TB) cell is also compared with that of the proposed cell.

Study on low rate of change characteristics of saturation output current of 28 nm UTBB FDSOI at 300 °C high-temperature

Partially-depleted silicon-on-insulator (PDSOI) MOSFETs with full dielectric isolation structure are widely used in the high temperature field of 225 °C, but affected by the threshold voltage and carrier mobility, the saturated output current has a rate of change as high as 24.9% at 25 °C–300 °C, which will reduce the working speed and accuracy of the analog circuit. This paper studies the high temperature output current characteristics of ultra-thin body and buried oxide (UTBB) fully-depleted silicon-on-insulator (FDSOI) MOSFETs with the 28 nm low voltage threshold structure. The experimental results show that when the gate voltage of the device is constant, the saturation current change of 28 nm short-channel FDSOI device is 1.93% in the temperature range from 25 °C to 300 °C, which is 12.9 times more stable than that of 0.13 μm PDSOI device, 4.5 times and 8.4 times higher than that of 0.3 μm and 2 μm long-channel FDSOI device. When the gate voltage of the device drifts from the zero-temperature coefficient (ZTC) point by ±10%–±20%, the output current change of the short-channel FDSOI device is still the lowest. It is proved by theory and simulation that the low temperature change rate of the carrier velocity of the short-channel FDSOI device is the main factor affecting the stability of the output current. From the analysis of the saturation current model and the ZTC operating point, reducing the gate operating voltage of the device or increasing the threshold voltage of the device can further improve the stability of the output current at high temperatures. The research in this paper proves that the 28 nm UTBB FDSOI device has good high temperature saturation current stability, which can well meet the output current stability requirements of high temperature analog circuits.

High-Powered RF SOI Switch With Fast Switching Time for TDD Mobile Applications

This paper presents a fast switching and high-powered single-pole double-throw (SPDT) switch for RF switch circuits, such as TRx antenna switches and frequency band (or operation mode) selection switches in mobile handset applications. For fast switching time and performances of the RF switch, we proposed a novel method that can “selectively” control the impedance of a gate biasing circuit (“high” or “low” impedance). The proposed SPDT switch use the low impedance of the gate biasing circuit for fast switching time and use the high impedance of the gate biasing circuit to avoid the degradation of the insertion loss and harmonics. The proposed SPDT switch has no additional bias and no large payment for size consumption. According to measurement results, the turn-on switching time of the proposed SPDT switch was <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.35~\mu \text{s}$ </tex-math></inline-formula> (at 2 GHz). The insertion loss, isolation, and return loss at 2 GHz were 0.16 dB, 47.1 dB, and 24 dB respectively. 2nd and 3rd harmonic levels at 25 dBm input power at 2 GHz were −88.7 dBm and −78.9 dBm, respectively. Power handling capability was 39.5 dBm of input power at 2 GHz. The designed SPDT switch was implemented in a 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> partially depleted silicon-on-insulator (PD-SOI) process.

Design and Performance Analysis of Partially Depleted and Fully Depleted Silicon on Insulator MOSFET

In this paper, Partially Depleted Silicon on Insulator (PDSOI) MOSFET and Fully Depleted Silicon on Insulator (FDSOI) MOSFET are designed, and the impact of n-type doping concentration, work function variation, gate oxide, and silicon layer thickness on the performance of the device is studied and analyzed. The floating body and associated kink effects present in a PDSOI device are also investigated in detail. In addition to this, comparisons are made between PDSOI and FDSOI MOSFET to analyze their performance for various device parameters. The threshold voltage rises with increasing Si surface thickness and source doping, according to the data found. The drain current increases as the N-type doping concentration develops in both PD and FDSOI MOSFETs, and conduction begins after a concentration of 3x1017 cm−3 for PD and 2x1017 cm−3 for FDSOI, before which conduction is not effective. For the same n-type doping concentration and gate work function, FDSOI has a higher drain current than PDSOI. FDSOI is better than PDSOI since it eliminates PDSOI’s defects and enhances its performance. The Silvaco Atlas-2D TCAD simulator is used to simulate the device using conventional architecture and models.

Investigation of the Combined Effect of Total Ionizing Dose and Time-Dependent Dielectric Breakdown on PDSOI Devices.

The combined effect of total ionization dose (TID) and time-dependent dielectric breakdown (TDDB) of partially depleted silicon-on-insulator (PDSOI) NMOSFET is investigated. First, the effect of TDDB on the parameter degradation of the devices was investigated by accelerated stress tests. It is found that TDDB stress leads to a decrease in off-state current, a positive drift in threshold voltage, and a reduction of maximum transconductance. Next, the degradation patterns of TID effect on the devices are obtained. The results show that the parameter degradation due to gamma radiation is opposite to the TDDB stress. Finally, the combined effect of TID and TDDB is investigated. It is found that the drift of the devices’ sensitive parameters due to TDDB stress decreases in a total dose of gamma radiation environment. The TDDB lifetime is shortened, but the pattern of gate current change remains unchanged. The failure mechanism of the gate oxide layer under TDDB stress is not changed after irradiation.

Investigation of Negative Bias Temperature Instability Effect in Nano PDSOI PMOSFET.

The Negative Bias Temperature Instability (NBTI) effect of partially depleted silicon-on-insulator (PDSOI) PMOSFET based on 130 nm is investigated. First, the effect of NBTI on the IV characteristics and parameter degradation of T-Gate PDSOI PMOSFET was investigated by accelerated stress tests. The results show that NBTI leads to a threshold voltage negative shift, saturate drain current reduction and transconductance degradation of the PMOSFET. Next, the relationship between the threshold voltage shift and stress time, gate bias and temperature, and the channel length is investigated, and the NBTI lifetime prediction model is established. The results show that the NBTI lifetime of a 130 nm T-Gate PDSOI PMOSFET is approximately 18.7 years under the stress of VG = −1.2 V and T = 125 °C. Finally, the effect of the floating-body effect on NBTI of PDSOI PMOSFET is investigated. It is found that the NBTI degradation of T-Gate SOI devices is greater than that of the floating-body SOI devices, which indicates that the floating-body effect suppresses the NBTI degradation of SOI devices.

The low threshold-voltage shift with temperature and small subthreshold-slope in 28 nm UTBB FDSOI for 300 °C high-temperature application

Partially depleted silicon-on-insulator (PDSOI) MOSFETs are widely used in 225 °C high-temperature electronic system applications with integrated circuits. But the process node stays at 0.5 µm for a long time and no further breakthrough can be achieved. This paper reports the high-temperature characteristics of 28 nm ultra-thin body and box fully depleted SOI (FDSOI) CMOS transistors with low threshold voltage (LVT) structure. Experimental results demonstrate that V t shift changes with temperature as low as 0.59 mV °C−1, the subthreshold slope (SS) is 145.35 mV dec−1 at 300 °C, and the related parameters are optimized by 3.7 times and 2.2 times respectively compared with 0.13 µm PDSOI. Combined with theoretical analysis, it is proved that the ultra-body FDSOI has an LVT drift rate and better SS than 0.13 µm PDSOI at high temperature. The advantage of this performance is mainly due to the difference between VT and β VT coefficients related to the back gate effect. Under negative back-gate bias, the I on/l off ratio can be increased by two orders of magnitude without affecting V t shift changes with temperature, this proves that the FDSOI is capable of high-temperature applications above 300 °C. This paper provides substantial support for future high-temperature system integrated circuits from the micro-scale to the nano-scale.

Demonstration of an UltraLow Energy PD-SOI FinFET Based LIF Neuron for SNN

In this article, partially depleted silicon on insulator (PD-SOI) FinFET based LIF neuron is demonstrated to mimic biological neuronal behaviour with aid of well-calibrated 3D TCAD simulation. The floating body effect of PD-SOI FinFET is used to store the holes generated by the impact ionisation (&#x2018;II&#x2019;), which exhibits the integration phenomenon and recombination manifests the leaky function. It shows 5.4 fJ of energy per spike, which is significantly lower than other FinFET based neurons reported till date. Moreover, it needs only 1.8 V of supply voltage, which is lower as compared to its equivalent bulk FinFET and PD-SOI MOSFET based LIF neurons. The proposed PD-SOI FinFET LIF neuron shows megahertz range of spiking frequency, that is <inline-formula><tex-math notation="LaTeX">$\sim 10 ^{5}$</tex-math></inline-formula>&#x00D7; higher than biological neuron (<inline-formula><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula>1-10 Hz). Furthermore, the effective area of the FinFET is optimized as 0.023 <inline-formula><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula>m<inline-formula><tex-math notation="LaTeX">$ ^{2}$</tex-math></inline-formula>. Thus, the proposed PD-SOI FinFET based LIF neuron is more attractive for large scale hardware implementation of SNN, due to its energy and area efficiency comparable with biological neuron along with CMOS compatibility.

Study on the high-temperature triggering and holding characteristics of PDSOI SCR devices

In this paper, the triggering and holding characteristics of electrostatic discharge (ESD) protection devices operating under various ambient temperatures ranging from 25 °C to 300 °C are investigated. The measured ESD protection devices were silicon-controlled rectifier (SCR) devices fabricated in 0.18-μm partially depleted silicon-on-insulator (PDSOI) technology. Measurements were conducted using the transmission line pulse (TLP) test system. The triggering voltage, VT1, and the holding voltage, VH, of the SCR devices show negative coefficient phenomenon with the increasing temperature. The similarities and differences between the triggering condition and the holding condition are analyzed in detail. The underlying physical mechanisms related to the effects of temperature on the VT1 and VH are provided by the assist of technology computer-aided design (TCAD) simulation.

A Highly Scalable Junctionless FET Leaky Integrate-and-Fire Neuron for Spiking Neural Networks

In this article, a highly scalable and CMOS compatible double-gate junctionless field-effect transistor (DG-JLFET)-based leaky integrate-and-fire (LIF) neuron is presented for the sub-20 nm gate length which is the smallest reported until now. Using well-calibrated 2-D TCAD simulations, we demonstrated that DG-JLFET LIF is able to mimic biological neuronal behavior. The DG-JLFET LIF neuron shows a low threshold voltage ( -0.31 V) for firing a spike and requires 1.14 pJ of energy per spike which is ~ 32× less than partially depleted silicon-on-insulator (PD-SOI) MOSFET LIF neuron. The proposed neuron needs only 0.4 V of supply voltage that is ~ 7×, 7.5×, 5×, and 2× lower as compared to its counterpart PD-SOI MOSFET, FinFET, L-shaped bipolar impact ionization MOS (LBIMOS), and Si NIPIN Diode-based LIF neurons, respectively. In addition, at a gate length of 10 nm the DG-JLFET LIF requires 0.07 pJ of energy per spike, which is ~ 500×, ~ 642×, and ~ 86× lower than that of the PD-SOI MOSFET, single MOSFET and Biristor based LIF neurons, respectively. Moreover, the DG-JLFET LIF neuron shows spiking frequency in the range of megahertz, which is ~5 orders high compared to the biological neuron. The absence of metallurgical junctions in DG-JLFET eases the fabrication complexity and cuts down the thermal budget requirement.

Trigger mechanism of PDSOI NMOS devices for ESD protection operating under elevated temperatures* *Project supported by the National Natural Science Foundation of China (Grant No. 61804168).

Trigger characteristics of electrostatic discharge (ESD) protecting devices operating under various ambient temperatures ranging from 30 °C to 195 °C are investigated. The studied ESD protecting devices are the H-gate NMOS transistors fabricated witha 0.18-μm partially depleted silicon-on-insulator (PDSOI) technology. The measurements are conducted by using a transmission line pulse (TLP) test system. The different temperature-dependent trigger characteristics of grounded-gate (GGNMOS) mode and the gate-triggered (GTNMOS) mode are analyzed in detail. The underlying physical mechanisms related to the effect of temperature on the first breakdown voltage V T1 are investigated through the assist of technology computer-aided design (TCAD) simulation.

Influence of Buried Oxide Si+ Implantation on TID and NBTI Effects for PDSOI MOSFETs

The total ionization dose (TID) effect and negative bias temperature instability (NBTI) effect of 130-nm partially-depleted silicon-on-insulator (PDSOI) MOSFETs fabricated on hardened wafers with silicon ion implantation and unhardened wafers are investigated. A TID-hardened PDSOI MOSFET up to 1 Mrad(Si) is obtained by Si+ implantation in buried oxide (BOX). The hardening benefits from the electron traps in the BOX introduced by Si+ implantation. Although the radiation hardening process has a rare impact on nominal electrical characteristics of the device before irradiation, it will affect the NBTI reliability, which is manifested as the decrease in the NBTI lifetime for the radiation-hardened devices. The energy distribution of positive charges built up during NBTI stress is obtained. It proves that more damage-related traps exist near the gate oxide/silicon interface for the radiation-hardened device, which accelerates the threshold voltage shift during the NBTI stress. This conclusion is also verified by the low-frequency noise characteristics.

Research on Negative Bias Temperature Instability Effects Under the Coupling of Total Ionizing Dose Irradiation for PDSOI MOSFETs

The degradation mechanisms for pMOSFETs from a 130 nm partially-depleted silicon on insulator (PDSOI) technology under the combined effects of total ionizing dose (TID) and negative bias temperature instability (NBTI) are investigated. The TID and NBTI related degradations show an opposite trend as gate oxide scaling, which implies the different traps are activated during irradiation and NBTI stress. The radiation-induced traps can affect the NBTI effect of pMOSFET, especially for the ON bias irradiation. The irradiated I/O pMOSFET shows a smaller threshold voltage shift than the un-irradiated device under the same NBTI stress at the early stress stage. It may be contributed to the enhanced Fowler-Nordheim electron injection during NBTI stressing after ON bias irradiation. But the irradiation also increases the time exponent $n$ from 0.11 to 0.13 for Core pMOSFETs and from 0.18 to 0.20 for I/O devices. It means that the NBTI degradations become worse after ON bias irradiation in a long time scale. This phenomenon is attributed to the change of trap characteristics caused by irradiation. As a result, the NBTI lifetime of Core device is reduced by nearly three orders of magnitude and the lifetime of I/O device is reduced by five times after ON bias irradiation at the rated operating voltage.

Back-End-of-Line-Based Resistive RAM in 0.13 μ m Partially-Depleted Silicon-on-Insulator Process for Highly Reliable Irradiation- Resistant Application

We demonstrated a resistive random access memory (RRAM) based embedded non-volatile memory (e-NVM) solution integrated in the 0.13 μm partially depleted silicon on insulator (PD-SOI) process. The memory devices show excellent reliability. It has good endurance up to <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> electrical cycles without any degradation in low resistance state (LRS) and high resistance state (HRS). It can retain the data up to <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> s even at 125 °C. Both the LRS and HRS show little variation. After γ-ray radiation with various total ionizing doses (TIDs), the memory characteristics of the device including resistance states, set/reset voltages are not significantly degraded, suggesting good anti-radiation capability. The proposed 1T1R device integrated in SOI process provides a potential candidate for those applications in radiation environments.

A Fractional-N Reference Sampling PLL With Linear Sampler and CDAC Based Fractional Spur Cancellation

In this article, a fractional- $N$ reference sampling phase-locked loop (PLL) (RSPLL) is presented. A capacitor-based digital-to-analog converter (CDAC) is implemented at the output of the reference sampling phase detector (RSPD) to cancel the divider quantization error in fractional mode. The RSPD is linearized by maintaining a constant discharge current from the sampling capacitor. Although the discharging current source may induce some noise compared to a sampling PD. However, its noise can be effectively suppressed with the high-gain setting for the RSPD when the loop is in lock. The linear range of RSPD can be programmed to cover the quantization error in a frac- $N$ mode without degrading the PLL in-band phase noise. To mitigate the nonlinearity of RSPD, the CDAC is implemented with a high-order cancellation scheme using only one capacitor array but multiple reference voltages. The prototype chip was fabricated in a 45-nm partially depleted silicon-on-insulator (PDSOI) CMOS process. The measurement showed an output frequency range covering 7.7–9.1 GHz with an integrated jitter (10 kHz–50 MHz) of 135 fs and an in-band fractional spur level of −55 dBc at an offset frequency of 50 kHz. The entire PLL consumes 4.5 mW and achieves an figure of merit (FoM) of −250.8 dB.