A Fractional-N Reference Sampling PLL With Linear Sampler and CDAC Based Fractional Spur Cancellation

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In this article, a fractional- $N$ reference sampling phase-locked loop (PLL) (RSPLL) is presented. A capacitor-based digital-to-analog converter (CDAC) is implemented at the output of the reference sampling phase detector (RSPD) to cancel the divider quantization error in fractional mode. The RSPD is linearized by maintaining a constant discharge current from the sampling capacitor. Although the discharging current source may induce some noise compared to a sampling PD. However, its noise can be effectively suppressed with the high-gain setting for the RSPD when the loop is in lock. The linear range of RSPD can be programmed to cover the quantization error in a frac- $N$ mode without degrading the PLL in-band phase noise. To mitigate the nonlinearity of RSPD, the CDAC is implemented with a high-order cancellation scheme using only one capacitor array but multiple reference voltages. The prototype chip was fabricated in a 45-nm partially depleted silicon-on-insulator (PDSOI) CMOS process. The measurement showed an output frequency range covering 7.7–9.1 GHz with an integrated jitter (10 kHz–50 MHz) of 135 fs and an in-band fractional spur level of −55 dBc at an offset frequency of 50 kHz. The entire PLL consumes 4.5 mW and achieves an figure of merit (FoM) of −250.8 dB.