A 7.7~10.3GHz 5.2mW -247.3dB-FOM Fractional-N Reference Sampling PLL with 2nd Order CDAC Based Fractional Spur Cancellation In 45nm CMOS

Abstract

In this paper, a fractional- N reference sampling PLL (RSPLL) is presented. To mitigate the frac-N induced quantization error, a capacitor digital-to-analog converter (CDAC) based canceller has been implemented at the reference sampling phase detector (RSPD) output. The RSPD is programmed to provide a detection range of one VCO cycle which is enough to cover the quantization error in frac-N mode. The CDAC is also reused as the sampling capacitor for RSPD. Additionally, a second order cancellation scheme is implemented with only one capacitor array and two reference voltages to compensate for the nonlinearity from RSPD. The prototype chip was fabricated in a 45 nm partially-depleted silicon-on-insulator (PDSOI) CMOS process. Measurement showed an output frequency range covering 7.7~10.3GHz with an integrated jitter (10kHz-10MHz) of 190fs and an in-band fractional spur level of-56dBc at an offset frequency of 625kHz. The entire PLL consumes 5.2mW and achieves a FoM of -247.3dB.