Abstract
This paper presents a novel switching scheme for an ultra-low energy charge-redistribution digital-to-analog converter (DAC) to be used in successive-approximation register (SAR) analog-to-digital converter (ADC). The proposed scheme employs unit capacitors for voltage sampling and charge redistribution. Compared with previously published capacitive DAC which uses the same unit size of capacitor array, the proposed DAC needed only 33% of the total switches. SPICE simulation results show that the average switching energy can be reduced by more than 50%. An 8-bit SAR-ADC using the proposed switch scheme is designed in Global foundries 65nm CMOS process. The power consumption of the capacitive DAC is 160 nW at 1.2V power supply and 100KS/s.
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