Parasitic Bipolar Action Research Articles

Abnormal drain current (ADC) effect and its mechanism in FD SOI MOSFETs

A new type of abnormal drain current (ADC) effect in fully depleted (FD) silicon-on-insulator (SOI) MOSFETs is reported. It is found that the drain current becomes abnormally large for specific front- and back-gate voltages. The drain current exhibits a transient effect due to the floating body behavior and no longer follows the conventional interface coupling theory for these specific front- and back-gate bias conditions. It is shown that the ADC can be generated by the combination of gate-induced drain leakage, transient effects, and parasitic bipolar transistor action in FD SOI MOSFETs.

Short channel effects in polysilicon thin film transistors

Short channel effects have been investigated in n-channel polysilicon thin film transistors. Transconductance degradation has been observed when reducing the channel length L and this effect has been explained with the presence of a parasitic resistance related to residual implant damage. Threshold voltage slighlty decreases for channel length around L=1 μm and simulations confirm that the roll-off of the threshold voltage is expected for L<1 μm. In the output characteristics a stronger kink effect has been observed at short L which, from a comprehensive analysis of the current components, can be attributed to an enhanced parasitic bipolar transistor action.

Kink effect in short-channel polycrystalline silicon thin-film transistors

Excess current, induced by impact ionization (kink effect) has been investigated in short-channel polysilicon thin-film transistors (TFTs). We have shown, both experimentally and by using two-dimensional (2-D) numerical simulations, that the output characteristics are substantially degraded by the kink effect as the channel length is reduced. In particular, we have shown that the excess current, triggered by the impact ionization and enhanced by the parasitic bipolar transistor action, scales nearly as L−2, thus making very difficult the downscaling of polysilicon TFTs. Such L dependence has been clarified through a detailed analysis of the current components obtained from 2-D numerical simulations. The analysis demonstrates that there are fundamental issues with the output characteristics, and it appears that the introduction of appropriate drain field relief structures will be necessary for the fabrication of short-channel polysilicon TFTs with high output impedance.

INTRODUCTION TO SOI MOSFETs: CONTEXT, RADIATION EFFECTS, AND FUTURE TRENDS

The context of SOI technology is briefly presented in terms of wafer fabrication, configuration/performance of SOI devices, and operation mechanisms in partially and fully depleted MOSFETs. Typical radiation effects, induced by single particles and cumulated dose, are evoked: BOX degradation, parasitic bipolar action, coupling effects, transistor latch, and back-channel conduction. The future of SOI is tentatively explored, by discussing the further scalability of SOI-MOSFETs as well as the innovating architectures proposed for the ultimate generations of SOI transistors.

Channel thickness dependence of breakdown dynamic in InP-based lattice-matched HEMTs

We have investigated, by using Monte Carlo simulations, the effects of channel thickness on the breakdown dynamics in InP-based lattice-matched HEMTs (LM-HEMTs). Breakdown is due to the parasitic bipolar action of holes generated by impact ionization and accumulated in the low electric field regions near the source. Our results show that channel shrinking results in an increase in time-to-breakdown values due to holes real-space-transfer effects occurring in thin channel devices. The breakdown behavior of thin-channel devices (channel thickness /spl les/20 nm) is dominated by the accumulation of holes in the InAlAs buffer layer; in thick-channel devices breakdown is due to the parasitic bipolar action of holes accumulating in the InGaAs channel. These results suggest a frequency dependence of breakdown which can be relevant for power rf device applications and/or in the study of device survivability to rf overstress.

A thorough investigation of hot-carrier-induced gate oxide breakdown in partially depleted N- and P-channel SIMOX MOSFETs

In this paper, the hot-carrier-injected oxide region in the front interfaces is systematically investigated for partially depleted silicon-on-insulator (PDSOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) devices fabricated on a SIMOX wafer. The gate oxide properties associated with channel hot-carrier effects are investigated and the hot-carrier-induced device degradations are analyzed using stress experiments with three main types of hot-carrier injections-maximum gate current, maximum substrate current and parasitic bipolar transistor action. Based on experimental results, the influence of these injected carriers on the gate oxide properties is clarified. As a matter of fact, NMOSFETs degradation mechanism is shown to be caused by hot holes injected into the drain side of the gate oxide, and electrons trapped in the gate oxide can accelerate the gate oxide breakdown. PMOSFETs degradation mechanism depends on the biasing conditions. For the first time, we conclude that the electrical characteristics of NMOSFETs are significantly different from that of PMOSFETs after the gate oxide breakdown. An extensive discussion of the experimental results is provided.

A study on hot-carrier-induced gate oxide breakdown in partially depleted SIMOX MOSFET’s

The hot-carrier-induced oxide regions in the front and back interfaces are systematically studied for partially depleted SOI MOSFET’s. The gate oxide properties are investigated for channel hot-carrier effects. The hot-carrier-induced device degradations are analyzed using stress experiments with three typical hot-carrier injection, i.e., the maximum gate current, maximum substrate current and parasitic bipolar transistor action. Experiments show that PMOSFET’s degradation is caused by hot carriers injected into the drain side of the gate oxide and the types of trapped hot carrier depend on the bias conditions, and NMOSFET’s degradation is caused by hot holes. This paper reports for the first time that the electric characteristics of NMOSFET’s and PMOSFET’s are significantly different after the gate oxide breakdown, and an extensive discussion of the experimental findings is provided.

Suppression of Parasitic BJT Action in Single Pocket Thin Film Deep Sub-Micron SOI MOSFETs.

AbstractA study of parasitic bipolar junction transistor effects in single pocket thin film siliconon-insulators (SOI) nMOSFETs has been carried out. Characterization and simulation results show that parasitic bipolar junction transistor action is reduced in single pocket SOI MOSFETs in comparison to homogeneously doped conventional SOI MOSFETs. A novel Gate-Induced-Drain-Leakage (GIDL) current technique was used to characterize the SOI MOSFETs. 2 - D simulations were carried out to analyze the reduced parasitic bipolar junction effect in single pocket thin film SOI MOSFETs.

Hot carrier induced degradation in mesa-isolated n-channel SOI MOSFETs operating in a Bi-MOS mode

A thorough investigation of hot carrier effects is made in mesa-isolated SOI nMOSFETs operating in the Bi-MOS mode (abbreviated as Bi-nMOSFETs). As a result of its unique hybrid operation mechanism, significant reduction of hot carrier induced maximum transconductance degradation and threshold voltage shift in the Bi-nMOSFET is observed in comparison with that in the conventional SOI nMOSFETs. Device lifetime of SOI Bi-nMOSFETs and conventional SOI nMOSFETs was roughly estimated for comparison. In view of the analysis of the degradation mechanism, the devices were stressed under different conditions. The post-stress body current and stress body current in Bi-nMOSFETs as a function of the stress time and stress drain voltage were evaluated as further proofs of the aging reasons. The hot electron injection is found to be the dominant degradation process in the SOI Bi-nMOSFETs. Compared with SOI nMOSFETs, SOI Bi-nMOSFETs show better immunity to the parasitic bipolar transistor action due to the body contact. In addition, the positive body bias can result in lowered hot hole injection into the gate oxide due to the provision of the generated hole leakage path, and thus decreased interface traps.

Study of the extended p/sup +/ dual source structure for eliminating bipolar induced breakdown in submicron SOI MOSFET's

Simulation results on a novel extended p/sup +/ dual source SOI MOSFET are reported. It is shown that the presence of the extended p/sup +/ region on the source side, which can he fabricated using post-low-energy implanting selective epitaxy (PLISE), significantly suppresses the parasitic bipolar transistor action resulting in a large improvement in the breakdown voltage. Our results show that when the length of the extended p/sup +/ region is half the channel length, the improvement in breakdown voltage is about 120% when compared to the conventional SOI MOSFET's.

Numerical Analysis of the Electrical Characteristics of Gate Overlapped Lightly Doped Drain Polysilicon Thin Film Transistors

Polycrystalline silicon (polysilicon) thin film transistor (TFT) technology is emerging as a key technology for active matix liquid crystal displays, allowing the integration of both active matrix and driving circuitry on the same substrate. However, conventional self-aligned polysilicon TFTs present several undesired effects in the electrical characteristics, including large off-currents, kink effect and hot carrier instabilities. These effects are related to the presence of high electric fields at the drain junction and drain field relief is essential. Among the different structures proposed to reduce the drain field, the gate overlapped lightly doped drain (GOLDD) structure appears to have a number of advantages. In this work we investigate the electrical characteristics of GOLDD polysilicon TFTs by using 2-dimensional (2D) numerical analysis. From a close analysis of the output characteristics, we have distinguished two saturation regimes: the first related to the conventional formation of the pinch-off region near the LDD, the second one, occurring at higher source-drain voltages, related to the depletion of the LDD region. Impact ionization effects have been also analysed and kink effect in GOLDD structure has been found to be associated with the parasitic bipolar transistor action, similarly to silicon-on-insulator (SOI) devices. At very high source-drain voltages, avalanche breakdown occurs, due to impact ionization occurring at both channel/LD-region and LD-region/n+ region junctions.

Suppression of parasitic bipolar action in ultra-thin-film fully-depleted CMOS/SIMOX devices by Ar-ion implantation into source/drain regions

This paper proposes a new technique that can effectively suppress the parasitic bipolar action (PBA) in ultrathin-film fully-depleted (FD)nMOSFET's/SIMOX with a floating body. In this technique, recombination centers are created in the source and drain (S/D) regions by deep Ar-ion implantation. They act to reduce the number of holes that accumulate in the body region by increasing the hole current flowing from the body region into the source region. Consequently, the rise of the body potential is lowered, and the parasitic bipolar action can be suppressed. A 0.25-/spl mu/m gate nMOSFET/SIMOX fabricated with an Ar dose of 2/spl times/10/sup 14/ cm/sup -2/ exhibited excellent improvements in electrical characteristics: a reduction in the off-leakage current of over two orders of magnitude and an increase in the drain-to-source breakdown voltage beyond 0.6 V.

Recombination Centers Created by Ar + ‐Ion Implantation into SIMOX Substrates

The characteristics of the defects created by ‐ion implantation into SIMOX substrates, to suppress the parasitic bipolar effect in a floating‐body n‐metal‐oxide‐semiconductor field effect transistor/SIMOX (n‐MOSFET/SIMOX) were investigated Secondary‐ion mass spectroscopy showed that implanted Ar atoms gathered in the top Si layer by annealing and their concentration decreased with increasing annealing temperature. No secondary defects were observed in the top Si layer by cross‐sectional transmission electron microscopy, when ions were implanted near the interface between the top Si layer and the buried oxide (BOX) layer. The implanted Ar atoms did not affect boron atoms, but they deactivated phosphorous atoms electrically. This deactivation is thought to form an argon‐phosphorous complex. Electron spin resonance measurements showed that the defects created in SIMOX substrates were paramagnetic defects called the Pb centers at the top‐Si/BOX interface. Therefore, it is concluded that an Ar atom itself does not form a recombination center and that the Pb centers created by implantation act as recombination centers preventing parasitic bipolar action in an n‐MOSFET/SIMOX.

Suppressing the parasitic bipolar action in fully-depleted MOSFETs/SIMOX by using back-side bias-temperature treatment

A new suppression method for parasitic bipolar action is presented for fully-depleted surface-channel nMOSFETs on SIMOX-structures by using the back-side bias-temperature (BSBT) treatment technique. After 10 h of BSBT treatment, increase in source-drain breakdown voltage of about 300 mV was obtained. A peculiar hot-carrier degradation is also suppressed and device lifetime is improved by 20 times. The device characteristics are not degraded by BSBT treatment because it induces a bias stress to back interface between the buried oxide and the active silicon layer, which does not affect the front channel. Influences of BSBT stress to the back interface were investigated using several methods. The suppression mechanism proposed is the generation of charges and interface traps at the back interface.

Impact of latch phenomenon on low-frequency noise in SOI MOSFETs

The low-frequency noise in fully (FD) and partially (PD) depleted SOI MOSFETs is experimentally investigated for channel lengths down to 0.1 μm. The noise is discussed in terms of carrier number and mobility fluctuations for a wide range of SOI structures. Furthermore, the influence of the latch effect on low-frequency noise is analyzed. It is found that the flicker noise is mainly caused by the carrier number fluctuations due to the dynamic trapping of electrons (or holes) by oxide interface traps in all the SOI devices. However, an excess noise is also obtained in the presence of a parasitic bipolar action.

Thin-film quasi-SOI power MOSFET fabricated by reversed silicon wafer direct bonding

A quasi-SOI power MOSFET has been fabricated by reversed silicon wafer direct bonding. In this power MOSFET, the buried oxide under the channel and source regions is removed and the channel region is directly connected to the source body contact electrode to reduce the base resistance of the parasitic npn bipolar transistor. The quasi-SOI power MOSFET can suppress the parasitic bipolar action and shows lower specific on-resistance than that of the conventional SOI power MOSFET. The fabricated chip level quasi-SOI power MOSFET shows the specific on-resistance of 86 m/spl Omega//spl middot/mm/sup 2/ and on-state breakdown voltage of 30 V.

SEU critical charge and sensitive area in a submicron CMOS technology

This work presents SEU phenomena in advanced SRAM memory cells. Using mixed-mode simulation, the effects of scaling on the notions of sensitive area and critical charge is shown. Specifically, we quantify the influence of parasitic bipolar action in cells fabricated in a submicron technology.

Suppression of Parasitic Bipolar Action and Improvement of Hot-Carrier Reliability in Fully-Depleted Metal-Oxide-Semiconductor Field Effect Transistors on SIMOX (Separation by IMplanted Oxygen) Introducing Recombination Centers near Source Junction

Fully-depleted metal-oxide-semiconductor field effect transistors (MOSFETs) fabricated on a SIMOX (Separation by IMplanted Oxygen) wafer are very promising devices for next-generation low-power high-speed LSIs. However, it is essential to suppress parasitic bipolar action in order to improve source-drain breakdown voltage for practical use in LSIs except for extremely low-voltage-operated applications of less than around 1 V. In this paper, a new suppression method of parasitic bipolar action is proposed, which uses recombination centers near the source junction. Using a two-dimensional (2-D) device simulator, the effects of recombination centers are analyzed, and an effective and stable position for the region containing recombination centers is clarified. Moreover, the effectiveness of the new method is experimentally verified using Ar ion-implantation into the source/drain regions, to introduce the recombination centers. The new method is also remarkably effective in improving hot-carrier reliability, because a hot-carrier degradation mode peculiar to MOSFETs/SOI is able to be suppressed by it.

Suppressing the parasitic bipolar action of SOI-MOSFETs by using back-side bias-temperature treatment

The improvements in the device characteristics of fully depleted nMOSFETs/SIMOX treated using a back-side bias-temperature treatment are presented This method suppresses the parasitic bipolar action without causing degradation of device characteristics. Suppression of parasitic bipolar action increases the source-drain breakdown voltage by about 500 mV and increases device lifetime under hot-carrier stress by a factor of 15. The effects of this treatment can be attributed to the generation of traps at the interface between the buried oxide and the active silicon layer.

Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high-current simulations

The design and optimization of ESD protection circuits is greatly enhanced by the ability to perform circuit-level simulations of the protection circuits and the I/O buffers. Most available simulators do not cover the high current region of the circuit operation, but still enable an approximate analysis to be made of the behaviour under ESD conditions. In this article, a description of the behaviour of the MOS device in the high current regime is presented together with the model equations governing that behaviour. The equations have been implemented into a SPICE circuit simulator, and the experimental and simulation results are given. A simple parameter extraction methodology is presented that uses the terminal currents from a single MOS DC I-V curve to obtain all the MOS and bipolar parameters required for the model.