Parasitic Bipolar Action Research Articles

High-Speed SOI 1/8 Frequency Divider Using Field-Shield Body-Fixed Structure

A high-speed silicon-on-insulator (SOI) 1/8 frequency divider with body-fixed structure was demonstrated using field-shield (FS) isolation. The maximum operation frequency is 2.1 GHz at 3.3 V. The SOI divider operates about 1.6 times faster than a bulk divider with the same dimensions. The normalized power consumption of the SOI divider at the maximum operating frequency is about 60% of that of the bulk divider. I d-V d transistor characteristics were improved, eliminating the kink in the saturation region, and the linearity of inverter characteristics was also improved with the body-fixed structure. The body contact collects excess carriers in the channel region, thereby preventing the parasitic bipolar action. From these results, it is suggested that devices using a field-shield body-fixed SOI structure have the potential for use in GHz-level systems containing analog circuits, and they are expected to be applied to portable communication systems and portable computers used in the multimedia era.

Reduction of parasitic bipolar transistor actionand punchthrough susceptibilityin MOSFETs using Si/Si 1-x Ge x sources and drains

Silicon CMOS devices are subject to some limitations as the dimensions are scaled down for VLSI applications. The incorporation of SiGe into the p-channel device can reduce parasitic bipolar action and punchthrough susceptibility. The authors compare the properties of elevated source and drain devices with and without Si/sub 1-x/Ge/sub x/ in the source and drain regions. We show that the parasitic bipolar gain is reduced by a factor of 18 and that the punchthrough effects seen in silicon devices are absent in the Si/sub 0.8/Ge/sub 0.2/ devices.

New hot-carrier-degradation mode in thin-film SOI nMOSFET's

A new hot-carrier degradation mode peculiar to MOSFET's fabricated on thin-film SOI is described. This degradation mode, which occurs in nMOSFET's more easily than in pMOSFET's, is due to suppression of parasitic bipolar action caused by recombination of excess carriers through hot-carrier-induced front interface-traps. Threshold voltage is significantly shifted by this phenomenon. The reliability lifetime defined by threshold voltage shift and drain current degradation is also discussed, considering the new degradation mode. >

Reliability of ultra-thin SOI MOSFET's

The hot-carrier-injected oxide regions in the front and back interfaces are systematically clarified for fully depleted surface-channel nMOSFET's and surface-channel and buried-channel pMOSFET's on SOI, which is essential to understand hot carrier reliability. The influence of these injected carriers on the front-channel properties is investigated. A new hot-carrier degradation mode peculiar to MOSFET's on SOI is described. This mode is caused by suppression of parasitic bipolar action due to hot-carrier-induced front interface traps. The reliability lifetime of nMOS and pMOSFET's is also discussed, considering the new degradation mode.

The use of body ties in partially depleted SOI MOSTs operating at cryogenic temperatures

In this paper, the use of a body tie in partially depleted SOI MOSTs operating at 4.2 K is critically discussed. It is shown that there is a considerable improvement in the threshold voltage metastability and the related hysteresis and transient behavior of the drain current. However, the typical floating body effects, like the kink and the parasitic bipolar action are hardly suppressed. This is mainly due to the high series resistance of the body contact, similar as in bulk MOSTs operated at liquid helium temperatures.

Source-to-drain breakdown voltage improvement in ultrathin-film SOI MOSFET's using a gate-overlapped LDD structure

A gate-overlapped LDD structure was introduced to ultra-thin SOI MOSFET's in order to overcome the degradation in source-to-drain breakdown voltage (BVds) due to a parasitic bipolar action. By reductions in drain electric field and parasitic resistance at a source n/sup -/ region, the BVds was improved with almost the same current drivability as that in single drain structure. The behavior of the BVds on LDD n/sup -/ concentration was investigated by use of a numerical device simulator, and it was found that the electric field at a lower portion of the n/sup -/ region, which forms the current path, was relaxed effectively at an optimum n/sup -/ doping condition. >

Analysis of drain breakdown voltage in enhancement-mode SOI MOSFETs

The mechanisms for drain breakdown (punchthrough, avalanche and snapback) are compared in bulk and SOI enhancement-mode MOSFETs. Because of parasitic lateral bipolar action, avalanche and snapback limit the usable drain voltage values in SOI devices well below the BV DS of bulk devices. In very short-channel devices (<0.35 ωm), however, punchthrough limits bulk transistors to a lower breakdown voltage than parasitic bipolar action does to SOI devices. This observation corroborates the idea that SOI might become a technology of choice for deep-submicrometer CMOS applications.

Non-isothermal analysis of breakdown in SOI transistors

Non-isothermal device simulation is used to calculate the drain characteristics of an SOI transistor. The breakdown voltage is found to be lower when lattice heating is accounted for, rather than higher, as the temperature dependence of the ionization coefficients would suggest. The results of numerical experiments show that this anomalous behavior is due to the temperature dependence of carrier injection caused by parasitic bipolar action. The lattice temperature in the source region thus has a major influence on breakdown behavior.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A fully integrated silicon-based 40-V thermal ink jet IC

A fully-integrated silicon-based thermal ink jet printhead which produces high speed, laser-quality printing at 300 spots per inch resolution is described. Monolithic integration of the 5-V logic circuitry, 13-V predriver circuitry, 40-V MOSFETs, and 192 n + polysilicon heater elements requires multiple process and device design trade-offs. The TIJ printhead is customer replaceable and must be protected from far greater static discharges than normal VLSI circuits. Design issues and failure mechanisms of the power MOSFETs and ESD protection devices are discussed. Two-dimensional simulations which include parasitic bipolar action and lattice heating illustrate the design concepts. Electrical characteristics of the 40-V power MOSFETs and 16-kV ESD protection devices are presented.

Multistable floating body potentials: The cause of hysteresis in silicon-on-insulator metal-oxide-semiconductor transistors

An experimental study of the hysteresis ID-VG characteristics in n-channel silicon-on-insulator metal-oxide-semiconductor transistors is reported. The result shows that the hysteresis is induced by multistable floating body potentials. An analytical model, which is based on the nonlinear feedback of carrier generation via multiplication and carrier discharge through parasitic bipolar action, also reveals that multistable floating body potentials are responsible for the hysteresis in ID-VG characteristics. To alleviate hysteresis effect, it is essential to reduce the parasitic bipolar current gain α and multiplication factor M. The reduction of α and M can be achieved by optimal source/drain design.

New physical model of multiplication-induced breakdown in MOSFETs

The thesis of this paper is that the mechanism of multiplication-induced breakdown is essentially different from what has previously been thought. Two consecutive phases of the breakdown: enhanced body effect (EBE) and parasitic bipolar action have to be distinguished. It is shown that the difference between the EBE and the ordinary body effect results from the fact that the body effect does not involve any electrical field, whereas EBE has to account for a nonzero field in the bulk, necessary to drive the substrate current. Similarly the bipolar action may be treated in terms of a parasitic bipolar transistor, but only on condition that the variable geometry and unconventional mode of biasing of the base are taken into account. It has been found that the size of the base increases considerably with V DS. In addition, the base bias V be is not equal to V sub − V sub = R sub I sub becomes entirely constant) but rather to V sub + δΨ − V SB, where δΨ has been explicitly related to the substrate current I sub. The new physical model of multiplication-induced breakdown has been verified and confirmed according to numerical simulation results. Furthermore, the analytical predictions based on it agree very closely with measured drain and substrate current characteristics.

Body current scanning: A novel technique for characterizing the floating body effects and parasitic bipolar action in silicon-on-insulator metal-oxide-semiconductor transistors

Body current scanning (BCS) is a new concept that exploits body (substrate) current reversal in NPN bipolar transistors to characterize the floating body effects and parasitic bipolar action in n-channel silicon-on-insulator (SOI) metal-oxide-semiconductor (MOS) transistors. At sufficiently high drain biases, a parasitic bipolar transistor modeled in parallel with the SOI MOS transistor is activated by hole accumulation in the body. BCS directly measures the floating body potential corresponding to the parasitic bipolar base, and is capable of distinguishing between the respective current contributions from MOS and bipolar devices. Consequently, the evaluation of parasitic bipolar and the influence of floating body on SOI device characteristics are facilitated.

Effects of channel width and parasitic bipolar action on p-type poly-Si resistor characteristics

The effects of channel width on I-V characteristics of thin-film p-type poly-Si resistors are discussed, in particular for the case in which the resistor current is mainly due to field-enhanced generation of carriers at the drain end (as can be common at high drain electric field). A significant decrease in current per unit width (microamperes per micrometer) is observed as the channel width is reduced from 3 to 0.6 mu m. This decrease in current per unit width is due to the influence of fixed positive charge along the channel edges, which decreases the beta value associated with parasitic bipolar action in this regime of device operation. >

An analytical model for snapback in n-channel SOI MOSFET's

An analytical snapback model for n-channel silicon-on-insulator (SOI) transistors with body either tied to the source or floating is been presented. The snapback is modeled as a nonlinear feedback system leading to negative transconductances from which the jump in current can occur at the point of instability. The crux of this model is based on the strong dependence of the transistor threshold voltage on the body potential when the body potential is above the transistor surface potential at strong inversion. No parasitic bipolar action is invoked to account for the snapback phenomena. The model correctly predicts the occurrence of hysteresis/latch phenomena and the conditions under which the current jump occurs despite some gross approximations in the electric field and the injection level. Results obtained from this model show good agreement with experimental data measured from SIMOX devices fabricated on 0.3- mu m epi film. >

Experiments and modeling of the photocurrent response of GaAs MESFETs

1- mu m technology GaAs MESFETs were exposed to a transient radiation environment at the Rensselaer Gaerttner linear accelerator laboratory and modeled by computer simulation using a modified version of the PISCES-IIB semiconductor device simulation code and the TRIGSPICE circuit simulation code. The MESFETs were tested in steady-state conditions, with short (20-ns) radiation pulses and with short pulses on devices that had received a prior dose of gamma, neutron, or neutron-plus-gamma irradiation. Parasitic bipolar action was observed in the short pulse testing in unexposed devices. Previously unreported transient failure was observed in the neutron preirradiated devices only. The threshold for this failure is consistent with the level of severity of prior irradiation. steady-state photocurrent and the parasitic bipolar transistor are modeled and explained on the basis of physical mechanisms. >

A simple technique to induce and control short pulses of deep drain-source breakdown conditions

A simple method to induce drain-source breakdown, followed by the parasitic bipolar action, is reported for time intervals and energies sufficiently small to avoid thermal runaway. A relatively large capacitor, connected in parallel to the device under test, is charged up using a sufficiently large resistor and discharges automatically as the breakdown voltage (BV/sub DSS/) is reached, thus eliminating the need for a fast and 'ringing-free' switch in the test setup. Since the discharge process is controlled by the small dynamic device resistance, rather than the large external resistor, the resulting transitions are fast enough and therefore compatible with electrostatic discharge (ESD) or latch-up turn-on conditions. Such pulses were successfully used to study soft ESD damage in lightly-doped-drain (LDD) devices, using simple on-wafer probing.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

MAXIMUM OPERATING VOLTAGE LIMITATIONS DUE TO PARASITIC BIPOLAR ACTION IN VLSI CMOS

The influence of the PBTA (Parasitic Bipolar Transistor Action) induced by impact ionization on the maximum operating voltages as well as on the isolation performance in VLSI CMOS structures was investigated using the sensitivity of the nMOS- and bipolar-parameters to the operating voltages. Strong coupling between the MOS-and bipolar-currents exists due to the potential drop caused by the impact ionization currents of the nMOSFET. The base currents of the bipolar transistors reduce the measurable substrate current. The maximum operating voltage in CMOS is limited by the impact ionization induced PBTA. The isolation performance is reduced by the collector current of the vertical transistor.

Computer simulation of ionizing radiation burnout in power MOSFETs

The first computer simulation of the ionizing-radiation-induced burnout in power MOSFETs is reported. The modeling results support a current-induced avalanche burnout mechanism at the interface of the epitaxial layer and the substrate coupled with parasitic bipolar transistor action, leading to secondary breakdown and thermal runaway. The simulations allow an evaluation of the effects of semiconductor parameters, device geometry, doping profiles, and bias voltage on the burnout dose-rate threshold. The model provides a method for optimizing the radiation hardness of power MOSFETs. >

Parasitic bipolar effects in submicrometer GaAs MESFET's

We report the observation for the first time of parasitic bipolar action in GaAs MESFET's. It manifests itself in the form of increased transconductance at higher drain voltage, abrupt change in output conductance (kink effect) around 4-V drain-source voltage, and a gate-voltage-dependent substrate current. These effects are explained by electron-hole pair generation in the high-field region at the drain. The holes generated are injected into the substrate where they form the base region of a parasitic lateral bipolar transistor. The effect also explains a new breakdown mechanism for short-channel enhancement-mode MESFET's.

Role of source N + N - structure in parasitic bipolar action of lightly doped short-channel MOSFETs

Theoretical and experimental evidence of the influence of N+N- source structures, encountered in state-of-the-art short-channel NMOSTs, on the value of the breakdown sustaining voltage is presented. It appears that, by increasing the distance between the high-low diffusion junction and the N-P metallurgical junction, one decreases the emitter (source) efficiency and also the current gain of the parasitic bipolar transistor. Taking this effect into account, the same value of breakdown sustaining voltage with a lower series source and drain resistivity may be achieved. This is shown experimentally.