MOSFET Parameters Research Articles

Comparison of Si CMOS and SiC CMOS Operational Amplifiers

In this study, we numerically compare the characteristics of Si and SiC CMOS operational amplifiers (OpAmp) using LTspice. According to prior researches, we set the device parameters for Si and SiC MOSFETs. The OpAmp consists of three stages: the input stage, the gain stage, and the output stage. We established three criteria for the OpAmp's operation: (1) a unity gain frequency of 1MHz, (2) an open-loop gain of at least 75dB, and (3) a phase margin of more than 60° when a load capacitance is 300pF. To achieve a unity gain frequency of 1MHz, we adjusted the values of the resistor and capacitor used for phase compensation. The supply voltage was set to be ±5V for the Si OpAmp and ±15V for the SiC one. Our numerical analysis of the frequency response shows that the Si OpAmp met all three criteria. In contrast, the SiC OpAmp, when faced with a load capacitor of 300pF, had a phase margin of 43.4°, falling below the 60° mark. For the SiC OpAmp, the frequency response declined rapidly when the supply voltage dropped to 10V or below.

Investigation of long channel bulkMOSFETsthreshold voltage model down to 10mKand key analog parameters at 4 K

AbstractThreshold voltage behavior at cryogenic temperatures is dominated by interface traps. This mechanism leads to different trends of the threshold voltage for NMOS and PMOS toward deep cryogenic temperature. This study investigates threshold voltage (Vth) at cryogenic temperatures down to 10 mK for the first time, based on the recently developed physical charge‐based analytical threshold voltage model. To investigate the impact of devices on circuits at low temperatures, crucial MOSFET and analog design parameters, including transconductance (gm), subthreshold swing (SS), linear region current (Ilin) andgm/IDSrelated parameters are characterized and compared from 300 to 4 K. A Discussion on circuit performance and power consumption has been conducted to provide useful insights for low‐temperature CMOS circuit design.

DFT-based Atomic Calculation of Si-doped HfO2 and Effect of its Negative Capacitance on Analog/RF, and VTC Parameters of MOSFET

DFT-based Atomic Calculation of Si-doped HfO2 and Effect of its Negative Capacitance on Analog/RF, and VTC Parameters of MOSFET

Impact of P-type doping and channel length on the performance of 2D SiC MOSFET

The performance of monolayer two-dimensional SiC MOSFET with various concentration of p-type doping in source/drain region and various lengths of channel were investigated based on the density-functional theory method. All MOSFETs could realize dynamic turn-off. The maximum ON-state current were up to 1152.8 μA/μm and 1731.4 μA/μm for 4.1 nm and 5.1 nm SiC MOSFET with 5 × 1020 cm−2 doping concentration, respectively, which could satisfy the requirement of the high-performance devices outlined by ITRS for production year 2028. In addition, the various parameters (transmission spectra, the intrinsic gate capacitance and so on) of MOSFETs were studied. Moreover，the LDOS and spectral current under ON-state voltage were researched to further explore the physical mechanism of the MOSFETs. Furthermore, the study found that the current increased as the temperature increasing, the current value and the temperature difference between left and right electrode at the fixed bias voltage and gate voltage were not related.

Adjustable Current Limiting Function With a Monolithically Integrated SiC Circuit Breaker Device

This paper proposes a current limiting function for a self-sensing and self-triggering monolithically integrated SiC circuit breaker device. The proposed function provides the device not only with a fast-response current breaking operation but also with the current limiting operation, including supplying a constant current to the load and preventing the detection of inrush currents. This function is suitable for replacing mechanical conductors in initial charging circuits within rectifiers and safety equipment in case of overcurrent phenomena. The proposed method achieves certain constant currents through a simple variation of the gate-drive circuit with the adjustable parameters of an additional MOSFET. The mechanism of the current limiting function is verified using TCAD simulations based on certain conditions. Consequently, experimental results verified that the circuit breaker device with the current limiting function reduces the inrush current by up to 76.9% using a 500 VDC distribution circuit system.

Investigation and Comparison of Temperature-Sensitive Electrical Parameters of SiC mosfet at Extremely High Temperatures

Due to the excellent silicon carbide (SiC) material characteristics, SiC MOSFETs can operate at extremely high temperatures and can be used in harsh environment applications. In this case, it is crucial to ensure the reliability of the power electronic systems. The temperature-sensitive electrical parameters (TSEPs) have been used for online junction temperature monitoring to monitor the health condition of the SiC MOSFET at low temperatures (<175℃). However, the performance of the TSEPs at extremely high temperatures is still unknown, and the influence of temperature on the TSEPs of SiC MOSFET at extremely high temperatures is unclear. In this article, the theoretical mechanisms of the impact of the extremely high temperature on TSEPs are investigated in detail. In particular, the different effects of high temperature on the turn-on delay time and turn-off delay time are discussed carefully. Based on the high-temperature characteristic test method proposed, the TSEPs of SiC MOSFET (including static and dynamic characteristics) are tested and analyzed comprehensively from room temperature to 375℃. And the sensitivity and linearity of the TSEPs in different temperature ranges are analyzed and compared. According to the results, threshold voltage and turn-off delay time are the two TSEPs with good sensitivity and linearity over a wide temperature range (from room temperature to 375℃). And the linearity of turn-off delay time is the best among all TSEPs over a wide temperature range.

Design of Novel Modified Double-Ended Forward Converter for Stepper Motor Drive

This paper presents the design and analysis of a modified double-ended forward converter (DEFC) for stepper motor-based robotic applications. The proposed converter topology provides galvanic isolation between the input and output while also higher efficiency with a smooth operative system, making it suitable for use in robotic systems that require both power and control signals to be transmitted. The paper also discusses the control strategy for the converter, which uses Proportional Integral (PI) to regulate the output voltage and current. The control strategy is implemented using a microcontroller-based system, which provides precise control of the output parameters. The converter is tested using a stepper motor-based load, and the results demonstrate the effectiveness of the proposed topology and control strategy. In addition to the experimental results, the paper also presents a detailed analysis of the converter’s performance. The analysis includes the input voltage and current, capacitor voltage, MOSFET parameters, output voltage and current, and calculation of efficiency. The analysis results show that the proposed converter topology and control strategy offer high efficiency comparing to existing converting approaches. Overall, the proposed double-ended forward converter offers a suitable solution for stepper motor-based robotic applications, providing efficient and reliable power and control signals. The results demonstrate the effectiveness of the proposed converter topology and control strategy, making it a promising option for use in future robotic systems.

Analytical modeling and doping optimization for enhanced analog performance in a Ge/Si interfaced nanowire MOSFET

This paper critically investigates the effect of doping on different device characteristics of a Ge/Si interfaced nanowire MOSFET (GSI-NWM) for analog performance enhancement. The doping of source, channel, and drain has a prominent effect on important device characteristics, which has been investigated through DC and AC analysis performed on the SILVACO TCAD simulator. A numerical computational-based simulation study has been used to investigate the modulation of various device characteristics, such as threshold voltage, cut-off frequency, subthreshold swing, MTPG, current ratio, channel resistance, and transconductance. The investigation revealed a strong dependence of most of these characteristics on the source, channel, and drain doping levels, providing valuable insights into device performance. Proper optimization in doping can significantly improve the performance of the device. A compact physics-based analytical model has been mathematically evaluated and proposed in this work, showing an excellent in-line agreement with the simulated results. This is a novel approach for improving the analog performance parameters of a nanowire MOSFET through doping optimization, which incorporates gate oxide stacking and germanium as a source material. In this work, the biosensing capability of the GSI-NWM has also been discussed and evaluated.

Superjunction Reliability Analysis Under Extreme High Positive and Negative Gate Voltage Stress

High gate stress test is an extremely important part of power device reliability test. On this basis, a 650 V super junction device is designed and fabricated, conventional stress test including high temperature gate bias (HTGB), high temperature reverse bias (HTRB) test results show that the device possess good reliability. The degradation of performance parameters under extreme high gate stress (including positive and negative) and the corresponding mechanism is further studied. It is found that the main performance parameters of superjunction MOSFET (SJ-MOSFET) will change significantly when the gate voltage stress is greater than 70 V. Under the positive high gate voltage stress, the threshold voltage decreases significantly. Under the negative high gate voltage stress, the threshold voltage also shifted to the left. Comparing the device under the same value of positive and negative high gate stress, it is found that the degradation degree of the device under positive stress is far greater than that under negative stress. Theoretical analysis combined with experimental data believes that the two degradation mechanisms are different. For positive stress, tunneling electrons collide on their way to the gate electrode creating electron–hole pairs, and the holes are captured by traps. But for negative gate voltage, holes tunnel and serve as extra gate positive charge directly. The electron injection efficiency is much higher than hole injection efficiency. Besides, the n-type region is larger at the bottom of the gate. Simultaneously, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{C}$</tex-math> </inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}$</tex-math> </inline-formula> measurement is also taken to prove the hypothesis.

A Novel Structure of Super-junction MOSFET with Improved Avalanche Energy Capability

The UIS characteristic of the device is a key parameter of the super-junction MOSFET, which represents the reliable performance of the device in the face of extreme conditions. The maximum avalanche energy (EAS ) that the device can withstand under a single pulse of the gate electrode or the maximum avalanche energy (EAR ) that the device can withstand under multiple pulses of the gate electrode is commonly used in the industry to characterize the UIS characteristic. To solve the avalanche energy problem of super-junction MOSFET, we propose a novel structure of super-junction MOSFET with a P-type diffused region on the top of the N-column drift region.

Investigation of Off-State Stress Induced Degradation of SiC MOSFETs Under Short-Circuit Condition

Investigation of SiC MOSFETs short-circuit (SC) degradation mechanism is critical to improve the overall reliability of power converters. At present, research on the SiC MOSFETs degradation mechanism mainly focuses on the on-state phase of the SC period. While, ruggedness of SiC MOSFETs in the off-state phase of short-circuit tests (SCTs) were neglected. In this paper, SiC MOSFETs degradation mechanism in the off-state phase of SCTs are investigated comprehensively. Specifically, distribution and magnitude of electrothermal stress of devices under test (DUTs) in the off-state phase of SCTs are analyzed by TCAD simulation. Which reveals two important phenomena: i) the device will suffer from long-term high temperature and high electric field stress in the off-state phase when negative turn-off gate voltage (Vgs-off) is applied; ii) high hole current in the channel region will last for several microseconds after the device is turned off. The observed SiC MOSFETs degradation in the off-state phase of SCTs is then proved by experiments, through which, the excessively low Vgs-off can reduce the SC capability of SiC MOSFETs is concluded. Moreover, the degradation results of static parameters of SiC MOSFETs are presented and the degradation mechanism is analyzed in detail.

Parameters Design and Optimization of SiC MOSFET Driving Circuit with Consideration of Comprehensive Loss and Voltage Stress

In conventional parameters design, the driving circuit is usually simplified as an RLC second-order circuit, and the switching characteristics are optimized by selecting parameters, but the influence of switching characteristics on the driving circuit is not considered. In this paper, the insight mechanism for the gate-source voltage changed by overshoot and ringing caused by the high switching speed of SiC MOSFET is highlighted, and we propose an optimized design method to obtain optimal parameters of the SiC MOSFET driving circuit with consideration of parasitic parameters. Based on the double-pulse circuit, we evaluated the influence of main parameters on the gate-source voltage, including driving voltage, driving resistance, gate parasitic inductance, and stray inductance of the power circuit. A SiC-based boost PFC is constructed and tested. The test results show that the switching loss can be reduced by 7.282 W by using the proposed parameter optimization method, and the over-voltage stress of SiC MOSFET is avoided.

THD Minimization and Reliability Analysis of Cascaded Multilevel Inverter

Inverters are DC to AC power converters that are widely used in AC motor drives and distributed energy generation systems. Multi-Level Inverters (MLIs) have emerged as the preferred inverter technology because of their advantages of reduced switching losses and better harmonic profile. This paper deals with the Minimization of Total Harmonic Distortion (MTHD) of Symmetric Cascaded H-bridge Multi-Level Inverter (SCMLI) and Asymmetric Cascaded H-bridge Multi-Level Inverter (ACMLI). A hybrid memetic algorithm composed of heuristic PSO (Particle Swarm Optimization) algorithm and traditional MAS (Mesh Adaptive direct Search) is proposed to optimize the switching angles. In Photo Voltaic (PV) system, the input DC voltage generally varies from its nominal value due to the change in temperature and irradiance. Thus, the sensitivity analysis of THD and harmonics is also carried out considering the variations with non-integer magnitudes of input DC sources. The experimental prototype of SCMLI and ACMLI topology is developed and validated with simulation results. The reliability and Mean Time to Failure (MTTF) of SCMLI and ACMLI are investigated based on power losses of the MOSFET and thermal parameters.

Implementation of class‐E/F3 power amplifiers based on the variations of the MOSFET grading coefficient, built‐in potential and output capacitance along with their roles in MOSFET selectivity

SummaryIn this paper, a theoretical analysis of the class‐E/F3 power amplifier based on the variation of the grading coefficient m1 and its vital role in MOSFET selectivity to operate safely under given design specifications is presented while the nonlinearity of the drain‐to‐source capacitance is considered. Moreover, the importance of Vbi and Cjo in designing the class‐E/F3 amplifier is investigated. To clarify how the grading coefficient m1 and the other mentioned parameters can directly influence the power amplifier performance and also its elements, these MOSFET parameters are considered as the independent variables of the calculated equations and consequently define the horizontal axis of the obtained plots. Accordingly, as the grading coefficient increases, the maximum switch voltage increases and values of the output power and output power capability decline. Moreover, to prove the reliability of the carried‐out analysis in selecting proper MOSFETs, the performances of three amplifier samples utilizing IRF510, IRFZ24N, and 2SK2504 MOSFETs with different grading coefficient m1 and almost similar Vbi and Cjo are studied. Then, by comparing the results of amplifiers with three MOSFETs, IRF510, IRF530, and IRF540, with similar grading coefficient and different values of Vbi and Cjo, the significance of considering the values of Vbi and Cjo is investigated. Eventually, three amplifiers with 2SK2504, IRF510, and IRF530 MOSFETs have been simulated, implemented, and tested and measurement results agreed well with the theoretical and simulation results.

Bridging the Gap between Design and Simulation of Low-Voltage CMOS Circuits

This work proposes a truly compact MOSFET model that contains only four parameters to assist an integrated circuits (IC) designer in a design by hand. The four-parameter model (4PM) is based on the advanced compact MOSFET (ACM) model and was implemented in Verilog-A to simulate different circuits designed with the ACM model in Verilog-compatible simulators. Being able to simulate MOS circuits through the same model used in a hand design benefits designers in understanding how the main MOSFET parameters affect the design. Herein, the classic CMOS inverter, a ring oscillator, a self-biased current source and a common source amplifier were designed and simulated using either the 4PM or the BSIM model. The four-parameter model was simulated in many sorts of circuits with very satisfactory results in the low-voltage cases. As the ultra-low-voltage (ULV) domain is expanding due to applications, such as the internet of things and wearable circuits, so is the use of a simplified ULV MOSFET model.

MOSFET-Based Memristor for High-Frequency Signal Processing

This research article proposes a floating memristor emulator configuration based on n-type MOSFETs only. The proposed memristor comprises three nMOS and an extra nMOS for an external grounded capacitor. Compared to the existing literature, the proposed floating MOS memristor enables a simple design without any sophisticated design complexity. The actual fingerprint of the memristor as a pinched hysteresis loop with different frequency domains and composite characteristics as incremental and decremental are well examined using computer simulation with 90-nm CMOS technology parameters for MOSFETs. The power consumed by the proposed circuit is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.6~\mu \text{W}$ </tex-math></inline-formula> . In addition, an experimental test using off-the-shelf components is investigated to verify the theoretical and simulated results. Moreover, the proposed nMOS-memristor emulator application is suitable for the modulation and demodulation of binary frequency-shift keying (BFSK) and Boolean logic gates.

Impact of Self-Heating on Linearity Performance of In0.53Ga0.47As-Based Gate-All-Around MOSFETs

In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As based gate-all-around (GAA) MOSFETs are very promising for high frequency applications because they deliver higher current and transconductance compared to their Si counterparts. In ultra-short GAA nanowire (NW) and nanosheet (NS) MOSFETs, heat accumulation in the channel region has become a serious issue as it raises the average lattice temperature several degrees above the ambient temperature ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{T}_{\text A}$ </tex-math></inline-formula> ). The increment in the average lattice temperature, also known as self-heating, degrades current driving capability and the linearity behaviour of the devices. In this work, the impact of self-heating on the linearity performance of In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As based GAA NW and NS MOSFETs has been investigated with the assistance of thermally calibrated TCAD simulation results. The effects of structural parameters of NW and NS MOSFETs, like gate oxide thickness (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OX</sub> ), the diameter of nanowire (d), the width of nanosheet (W), and the number of nanowires/nanosheets (N) on linearity performance have been extensively studied using the linearity figure of merits, such as VIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , and IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> . Moreover, the impact of self-heating mitigating techniques on the linearity performance of devices has also been explored in this work.

Analytical Model and Design of Voltage Balancing Parameters of Series-Connected SiC MOSFETs Considering Non-Flat Miller Plateau of Gate Voltage

Series connection is an attractive approach to increase the blocking voltage of SiC power MOSFETs. Currently, the voltage balancing design of the series connection of the SiC MOSFETs highly relies on offline calibration and is challenging in the complex field operation. In this paper, a quantitative model to assess the voltage balancing performance is proposed to achieve a clear mathematical interpretation of the dynamic response of the voltage imbalance control loop. To begin with, an analytical model of the drain-source voltage rising time during the turn-off transient concerning the non-constant Miller plateau is proposed. Based on the turn-off model of the single device, the voltage imbalance sensitivity (VIS) is proposed to describe the influence of the parameters on the gate driving signals on the voltage imbalance. The VIS parameter can be easily achieved from the behavior of single devices, abandoning the complex variables in series connection. Further, for the typical case, active time delay voltage balancing methods are selected to demonstrate the application of the VIS analysis method. Based on VIS, the accurate close-loop design is proposed for controlling the delayed time among the devices. The proposed analysis and method are verified in simulation and experiment. The paper offers a generalized approach to assess the performance and the design of the series connection of the SiC MOSFETs, which can be further applied in many other methods for parameter design and engineering applications.

On-chip leakage current variation measurement using external-reference-free current-to-time conversion for densely placed MOSFETs

This paper proposes a time-domain leakage current measurement circuit that uses an external-reference-free current-to-time conversion. Our proposed current-to-time converter (CTC) utilizes a dual inverter-based conversion to provide a stable reference. We share the CTC among the devices under test (DUTs) for accurate characterization of variation. Our CTC, along with a tree-based switch structure, allows us to densely place and route the DUT transistors using a cell-based design flow similar to a digital circuit design. We demonstrate our circuit by measuring subthreshold leakage currents of 256 minimum sized nMOSFETs in a 65 nm bulk low-power CMOS process. We could successfully extract the variations in subthreshold coefficient and subthreshold leakage current at different temperatures. Our circuit is also robust to supply voltage fluctuation making the circuit suitable for accurate characterization of MOSFET parameters for subthreshold operation.

Modeling and Suppression of the Crosstalk Issue Considering the Influence of the Parasitic Parameters of SiC MOSFETs

Due to the extremely fast switching speed of the SiC MOSFET, its crosstalk issue is more serious than that of the Si IGBT. Therefore, in order to ensure the reliability of the SiC MOSFET converters, the crosstalk problem must be solved firstly. Most of the existing crosstalk suppression methods are aimed at decreasing the crosstalk voltage introduced by the parasitic gate-drain capacitance (Miller capacitance), ignoring the influence of other parasitic parameters on the crosstalk voltage, such as the common source inductance, which may also lead to more serious reliability problems. Thus, this paper firstly establishes the mathematical model of the switching process of the SiC MOSFET half-bridge inverter. Then, the effects of various parasitic parameters (the gate-source capacitance, the gate-drain capacitance, the common source inductance, the gate inductance, the drain inductance) on the crosstalk voltage are analyzed and modeled in detail, which is verified by experiments. Based on the analyses and models, a novel crosstalk voltage suppression circuit is proposed, which can not only suppress the crosstalk caused by the gate-drain capacitance, but also solve the crosstalk issue considering the influence of other parasitic parameters, such as the common source inductance. Finally, a double pulse test platform is established to verify the effectiveness of the designed crosstalk suppression circuit under different voltage/current conditions.