Abstract
The UIS characteristic of the device is a key parameter of the super-junction MOSFET, which represents the reliable performance of the device in the face of extreme conditions. The maximum avalanche energy (EAS ) that the device can withstand under a single pulse of the gate electrode or the maximum avalanche energy (EAR ) that the device can withstand under multiple pulses of the gate electrode is commonly used in the industry to characterize the UIS characteristic. To solve the avalanche energy problem of super-junction MOSFET, we propose a novel structure of super-junction MOSFET with a P-type diffused region on the top of the N-column drift region.
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