Abstract

In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As based gate-all-around (GAA) MOSFETs are very promising for high frequency applications because they deliver higher current and transconductance compared to their Si counterparts. In ultra-short GAA nanowire (NW) and nanosheet (NS) MOSFETs, heat accumulation in the channel region has become a serious issue as it raises the average lattice temperature several degrees above the ambient temperature ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{T}_{\text A}$ </tex-math></inline-formula> ). The increment in the average lattice temperature, also known as self-heating, degrades current driving capability and the linearity behaviour of the devices. In this work, the impact of self-heating on the linearity performance of In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As based GAA NW and NS MOSFETs has been investigated with the assistance of thermally calibrated TCAD simulation results. The effects of structural parameters of NW and NS MOSFETs, like gate oxide thickness (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OX</sub> ), the diameter of nanowire (d), the width of nanosheet (W), and the number of nanowires/nanosheets (N) on linearity performance have been extensively studied using the linearity figure of merits, such as VIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , and IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> . Moreover, the impact of self-heating mitigating techniques on the linearity performance of devices has also been explored in this work.

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