Abstract
Although ultra-scaled III–V Gate-all-around (GAA) nanowire (NW) MOSFETs have been studied for their immunity to short channel effects, the degradation mechanisms, such as, hot carrier injection (HCI) in the NW MOSFETs are yet to be studied systematically. In this paper, we examine how HCI affects the NW device performance (ΔV <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> , ΔSS in both stress and recovery) at different bias conditions, and demonstrate that, unlike positive bias temperature instability (PBTI) in NMOS transistors, the HCI degradation is dominated by charge trapping. We analyze the implications of spatial charge trapping on device performance through experiments and simulation. We find that the distinctive features of HCI degradation of GAA NWs structure can be consistently interpreted by a Sentaurus™-based TCAD simulation.
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