Abstract
Series connection is an attractive approach to increase the blocking voltage of SiC power MOSFETs. Currently, the voltage balancing design of the series connection of the SiC MOSFETs highly relies on offline calibration and is challenging in the complex field operation. In this paper, a quantitative model to assess the voltage balancing performance is proposed to achieve a clear mathematical interpretation of the dynamic response of the voltage imbalance control loop. To begin with, an analytical model of the drain-source voltage rising time during the turn-off transient concerning the non-constant Miller plateau is proposed. Based on the turn-off model of the single device, the voltage imbalance sensitivity (VIS) is proposed to describe the influence of the parameters on the gate driving signals on the voltage imbalance. The VIS parameter can be easily achieved from the behavior of single devices, abandoning the complex variables in series connection. Further, for the typical case, active time delay voltage balancing methods are selected to demonstrate the application of the VIS analysis method. Based on VIS, the accurate close-loop design is proposed for controlling the delayed time among the devices. The proposed analysis and method are verified in simulation and experiment. The paper offers a generalized approach to assess the performance and the design of the series connection of the SiC MOSFETs, which can be further applied in many other methods for parameter design and engineering applications.
Highlights
The applications of medium voltage (MV) high power converters are rapidly growing in smart grids, motor drives, supercharge stations, and many other applications
It is demonstrated that the voltage imbalance in the series-connected device can be theoretically modeled and controlled, which supports the design of the voltage imbalance loop
A quantitative close-loop design of the voltage balancing of the series connection of SiC power MOSFETs is proposed in this paper
Summary
The applications of medium voltage (MV) high power converters are rapidly growing in smart grids, motor drives, supercharge stations, and many other applications. At t0, the device starts to turn off, the gate-source voltage decreases from Vg_on to the beginning of the Miller plateau voltage In this stage, SiC MOSFET operates in the linear region. SiC MOSFET operates in the linear region This stage ends when gate-source voltage cannot support the output current IL and the device enters the saturation region. The above equation contains only two unknown parameters, namely the voltage rising time trv and the gate-source voltage decreasing slope k They can be directly acquired by solving the equation. The parameters in the calculation come from the datasheet or the characterization test of the SiC MOSFETs. The turn-off drain voltage rising time will be adopted as the link between the voltage imbalance and the gate driver time delay, which will be discussed
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