P-channel MOSFETs Research Articles

Valence band structure of biaxial strained Germanium for hole transport calculation

A comprehensive study of hole mobility in Germanium material dependence on strained substrate orientations and carrier transport directions was performed in this paper. The heavy hole, light hole, and spin–orbit bands are included in the calculation of valence band structure. The biaxial strain induced valence band edge energy splitting and effective mass change were evaluated as well as their impacts on the hole mobility in Germanium were analysed. The results show that the optimum strained substrate orientation and carrier transport direction configuration are biaxial compressive strained on the (110) oriented substrate and in-plane as a hole transport direction, the configuration of which has the maximum hole mobility under the same strained level in comparison with others. The reason for high hole mobility is also explored. The current research is helpful to design the high performances p-channel MOSFETs in the strained Germanium system. The hole mobility of Germanium versus strain level under different biaxial strained substrate and transport directions configurations

Hydrogen-Terminated Diamond MOSFETs Using Ultrathin Glassy Ga2O3 Dielectric Formed by Low-Temperature Liquid Metal Printing Method

The p-type surface conductivity of hydrogen-terminated diamond (H-diamond) provides a viable approach toward diamond-based wide-bandgap metal-oxide-semiconductor field-effect transistors (MOSFETs) for high-power and high-frequency electronics. A facile, low-cost, and low-temperature method to form gate dielectrics on diamond that also preserves the integrity of hydrogen-termination is highly desirable for high-performance diamond surface electronics with process flexibility and high yield. In this work, we demonstrate a p-channel diamond MOSFET with an ultrathin glassy Ga2O3 dielectric layer derived from liquid metal. A liquid metal printing method was employed to transfer an amorphous Ga2O3 layer over the desired active p-channel region of H-diamond at low temperature, allowing the protection and preservation the hydrogen-terminated surface while also forming an efficient gate dielectric. The results of this work suggest that the liquid metal method can provide an efficient, low-cost, and high-yield pathway to form high-quality dielectrics for diamond-based transistors.

Double-Gate RESURF Lateral Insulated Gate Bipolar Transistor With Built-In p-Channel MOSFET for Active Conductivity Modulation Control Throughout Drift Region

A double-gate RESURF lateral IGBT (DGR-LIGBT) with build-in p-channel MOSFET (p-MOSFET) is proposed and studied by numerical TCAD simulations. In the conventional LIGBTs, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {ON}}$ </tex-math></inline-formula> is reduced by conductivity modulation in drift region. However, the stored minority carriers lead to high turn-off lose ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {OFF}}$ </tex-math></inline-formula> ). In the proposed DGR-LIGBT, the RESURF region is connected to the p-body via the built-in p-MOSFET. The primary gate switches the DGR-LIGBT between on- and off-states. In the on-state, a positive auxiliary gate voltage is applied to turn off the p-MOSFET; the RESURF region is disconnected from the p-body. Thus, the DGR-LIGBT works in fully modulated state and maintains a low <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {ON}}$ </tex-math></inline-formula> . Before the turn-off transient, the auxiliary gate voltage is pre-switched to a negative voltage to turn on the p-MOSFET, which electrically connects the RESURF region to the grounded p-body and extracts holes in the entire drift region. Therefore, the conductivity modulation throughout the drift region is suppressed, resulting in low <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {OFF}}$ </tex-math></inline-formula> .

Improved Electrostatics through Digital Etch Schemes in Vertical GaSb Nanowire p-MOSFETs on Si.

Sb-based semiconductors are critical p-channel materials for III–V complementary metal oxide semiconductor (CMOS) technology, while the performance of Sb-based metal-oxide-semiconductor field-effect transistors (MOSFETs) is typically inhibited by the low quality of the channel to gate dielectric interface, which leads to poor gate modulation. In this study, we achieve improved electrostatics of vertical GaSb nanowire p-channel MOSFETs by employing robust digital etch (DE) schemes, prior to high-κ deposition. Two different processes, based on buffer-oxide etcher (BOE) 30:1 and HCl:IPA 1:10, are compared. We demonstrate that water-based BOE 30:1, which is a common etchant in Si-based CMOS process, gives an equally controllable etching for GaSb nanowires compared to alcohol-based HCl:IPA, thereby realizing III–V on Si with the same etchant selection. Both DE chemicals show good interface quality of GaSb with a substantial reduction in Sb oxides for both etchants while the HCl:IPA resulted in a stronger reduction in the Ga oxides, as determined by X-ray photoelectron spectroscopy and in agreement with the electrical characterization. By implementing these DE schemes into vertical GaSb nanowire MOSFETs, a subthreshold swing of 107 mV/dec is obtained in the HCl:IPA pretreated sample, which is state of the art compared to reported Sb-based MOSFETs, suggesting a potential of Sb-based p-type devices for all-III–V CMOS technologies.

Fabrication of inversion p-channel MOSFET with a nitrogen-doped diamond body

A normally-off inversion p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a nitrogen (N)-doped diamond body deposited using microwave plasma-enhanced chemical vapor deposition (MPECVD) was fabricated. The MOSFET exhibited a drain current density of −1.7 mA/mm. Thus far, this value is similar to the device performance of the inversion p-channel MOSFET fabricated using a phosphorus (P)-doped n-type diamond body. The N2 used for N-doping is safer than the PH3 used for P-doping; moreover, the doping concentration is highly controllable. Because the MOSFET, which is a classical electronic device, is driven by a gate voltage, smooth functioning was possible even at a deep donor level. The observed characteristics of the classic MOSFET operating via an N-doped body are crucial for the development of diamond power devices. In this paper, we discuss the significance of the N-doped diamond body and electrical characteristics of the inversion p-channel MOSFET fabricated using an N-doped diamond body.

Demonstration of 4H-SiC CMOS circuits consisting of well-balanced n- and p-channel MOSFETs fabricated by ultrahigh-temperature gate oxidation

Complementary metal-oxide-semiconductor inverters featuring steep voltage-transfer characteristics (VTC) were successfully fabricated on 4H-SiC(0001) substrates. Even without nitridation of the MOS interfaces, well-balanced n- and p-channel field-effect transistors were realized by means of ultrahigh-temperature gate oxidation (HTO) at 1600 °C under reduced oxygen partial pressure. Improvements in the performances of both n- and p-channel SiC metal-oxide-semiconductor field-effect transistors were achieved by subsequently performing forming gas annealing (FGA) at 1200 °C, leading to mostly symmetric VTC with negligible hysteresis. The effect of HTO and subsequent FGA at high temperatures was verified from the stable and improved performance of 23-stage ring oscillators over a wide temperature range.

Analysis of Mobility for 4H-SiC N/P-Channel MOSFETs Up To 300 °C

The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> characteristics of 4H-SiC N/P-channel MOSFETs have been carried out at high temperatures up to 300 °C. Different scattering mechanisms of surface mobility for 4H-SiC N-channel MOSFETs have been studied in this article. Moreover, the temperature dependencies of various scattering mobilities for P-channel MOSFETs are given for the first time. Their temperature dependencies were simulated and analyzed at a temperature ranging from 27 °C to 300 °C. Furthermore, an improved method of extracting trapped charge from transfer characteristic is proposed, such that the density of occupied interface traps in a strong inversion can be extracted. The analysis of experimental results shows that sacrificial oxidation can decrease the occupied interface traps at high temperatures but not much effective at room temperature, and the Coulomb scattering in 4H-SiC P-channel MOSFETs has always been the main mechanism from 27 °C to 300 °C, which is different from 4H-SiC N-channel MOSFETs.

Investigation on threshold voltage of p-channel GaN MOSFETs based on p-GaN/AlGaN/GaN heterostructure* *Project supported by the Key-Area Research and Development Program of Guangdong Province, China (Grant Nos. 2020B010174001 and 2020B010171002), the Ningbo Science and Technology Innovation Program 2025 (Grant No. 2019B10123), and the National Natural Science Foundation of China (Grant No. 62074122).

The threshold voltage (V th) of the p-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) is investigated via Silvaco-Atlas simulations. The main factors which influence the threshold voltage of p-channel GaN MOSFETs are barrier height Φ 1,p, polarization charge density σ b, and equivalent unite capacitance C oc. It is found that the thinner thickness of p-GaN layer and oxide layer will acquire the more negative threshold voltage V th, and threshold voltage |V th| increases with the reduction in p-GaN doping concentration and the work-function of gate metal. Meanwhile, the increase in gate dielectric relative permittivity may cause the increase in threshold voltage |V th|. Additionally, the parameter influencing output current most is the p-GaN doping concentration, and the maximum current density is 9.5 mA/mm with p-type doping concentration of 9.5 × 1016 cm−3 at V GS = –12 V and V DS = –10 V.

Charge Trapping and Transconductance Degradation in Irradiated 3-D Sequentially Integrated FDSOI MOSFETs

Total-ionizing-dose (TID) effects are compared in 1) conventional high-temperature processed planar fully-depleted silicon-on-insulator (FD-SOI) p-channel MOSFETs, 2) 3-D sequentially integrated (3DSI) FD-SOI MOSFETs in the bottom layer with additional thermal budget and process flows due to the creation of the top layer, and 3) 3DSI low-temperature-processed FD-SOI MOSFETs in the top layer. When irradiated under worst case negative bias, 3DSI bottom-isolated transistors show significantly enhanced charge trapping and transconductance degradation than planar devices. The enhanced degradation for bottom-isolated devices is attributed primarily to increased interface- and border-trap formation at the buried oxide (BOX)/Si interface and/or lateral charge nonuniformities in the BOX. The radiation-induced transconductance degradation in top-isolated devices is attributed to the increased resistance of the portion of the channel that underlies the source/drain spacers.

Improvement of Both n- and p-Channel Mobilities in 4H-SiC MOSFETs by High-Temperature N₂ Annealing

Effects of high-temperature (1400 °C–1600 °C) N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> annealing on the interface states of 4H- SiC/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and the channel mobility of 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) were investigated. It is demonstrated that high-temperature N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> annealing is effective not only for the reduction of the interface state density near the conduction band edge but also for that near the valence band edge. N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> annealing improves channel mobility of both n- and p-channel MOSFETs as in the case of nitric oxide (NO) annealing. In particular, the field-effect mobility of the p-channel MOSFETs annealed in an N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ambient was improved to 17 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs, which is 30% higher than that of NO-annealed MOSFETs. The interface state density estimated from the subthreshold slopes in the MOSFETs is much higher than that extracted by the high–low method but is almost comparable to that estimated by the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\psi _{\text {s}}$ </tex-math></inline-formula> method in both the cases of interface states near the conduction and the valence band edges. These results suggest that there exist fast states (>1 MHz) near the valence band edge, and these fast states affect the channel mobilities of p-channel SiC MOSFETs as in the case of n-channel MOSFETs.

Voltage stress induced interface states and hole trapping in germanium pMOSFETs with high-k gate dielectric and metal-gate electrode

In this work, p-channel MOSFETs with the metal-gate electrode and high-k gate stack of ZrO2/Al2O3/GeO2 on n-Ge substrate are fabricated and investigated. The interface state generation (ΔNit) and hole trapping (ΔNot) during voltage stresses are examined. According to the time dependence on the subthreshold swing and the threshold voltage, both ΔNit and ΔNot can be extracted during the gate voltage stresses, which is characterized by the power-low (tn) model. The time exponent of ΔNit is in the range of 0.48-0.65 which is approximately two times that of ΔNot. Based on the Si/oxide model, the charged H+ diffusion may be the dominant process in the degradation of interface states. In the early stressing, the device degradation of threshold voltage shift mainly results from the hole trapping in the gate dielectrics. However, the long-term trend indicates that ΔNot will be overwhelmed by ΔNit after a characteristic time (tc). This implies, for the device degradation during gate voltage stresses, the contribution of ΔNot decreases with time, meanwhile, the contribution of ΔNit increases with time. According to the experimental results, the characteristic time is approximately independent of stress voltage and is about 106 s.

Inversion channel MOSFET on heteroepitaxially grown free-standing diamond

We successfully fabricated the inversion-type p-channel metal–oxide–semiconductor field-effect transistor (MOSFET) on heteroepitaxially grown free-standing diamond using silicon-based substrates. The drain current–drain voltage (Ids–Vds) and drain current–gate voltage (Ids–Vgs) characteristics were examined. The maximum drain current density and the peak field effect mobility (μFE) were around 0.35 mA/mm and 2.7 cm2 V−1s−1, which were lower than our reported results of the homoepitaxial diamond MOSFETs fabricated on high-pressure, high-temperature (HPHT) substrates. The interface state density (Dit) extracted from the subthreshold region was around 5.5 × 1012 cm−2eV−1, comparable to our reported results of the homoepitaxial diamond MOSFET. To further examine the reason for the low μFE, atomic force microscopy (AFM) measurements were performed for the n-type body of the heteroepitaxial diamond MOSFET, and we found that the surface roughness was much larger than our reported ones of the homoepitaxial diamond MOSFET. It can be deduced that the surface roughness would be one main limiting factor for the field effect mobility of the heteroepitaxial diamond MOSFET. The imperfect diamond heteroepitaxy would also degrade the field effect mobility. This work explores the potential of the inversion-type p-channel heteroepitaxial diamond MOSFETs, which would facilitate the practical application of diamond power devices.

TCAD Framework for HCD Kinetics in Low VD Devices Spanning Full VG/VD Space

The time kinetics of hot carrier degradation (HCD) is modeled using a reaction diffusion drift (RDD) framework. It is incorporated into Sentaurus Device TCAD and validated using conduction mode HCD data in n- and p-channel MOSFETs and FinFETs. RDD-enabled TCAD calculates carrier-energy-initiated generation of interface traps (ΔN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT</sub> ) and the impact of the resulting localized charges on device parametric drift. HCD at various gate (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) and drain (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> ) biases spanning various modes (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ≤ and > V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> ) are simulated for low stress V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> (<; 3 V). The self-heating (SH)-effect-induced temperature (T) increase is invoked for FinFETs. Data from various experiments are analyzed and a wide range of power-law time kinetics slope (n) is explained.

Simulation of the Nanoscale Joint Surrounding Gate SOI MOSFET Characteristics

In order to solve the current problem of increasing the efficiency of modern electronic circuits, the applicability of a nanoscale joint surrounding gate MOSFET with oval work area is discussed. The design and principle of its operation are considered. This concept involves of jointing the working areas of n-channel and p-channel MOSFETs. In fact, the JSMOSFET consists of two "glued" along the halves of MOSFETs: one - nchannel and the other - p-channel, but with one common gate. We analyze the applicability of the design of an oval-shaped protected area. In our case, the contact of two heterogeneously doped regions occurs in the plane passing through the small axis of the oval. The main channels are formed in zones associated with the large axis of the oval. This achieves the main goalincreasing the number of charge carriers. At the same time, the efficiency of short-channel effect suppression is maintained and a high current level of the transistor is provided in the strong inversion mode. By the developed TCAD model of a nanoscale joint surrounding gate MOSFET with an oval work area the electrophysical characteristics of several prototypes with different transverse dimensions were numerically calculated at a supply voltage of 0.5 V. From the simulation results, it follows that all prototypes are low-voltage devices that can function at voltages below 0.5 V in the gigahertz frequency range with a high gain. The proposed devices perform the function of inverting the input signal without distortion. From the comparison of modeling data, the scope scaling capabilities are determined. The obtained results create prerequisites for the development of the proposed transistor architecture, since electronic chips created on their basis will differ in low power supply voltage, high performance, and minimal occupied area, which meets modern requirements for transistors for analog and digital applications.

Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters

In this study, conventional CMOS and complementary field-effect transistor (CFET) inverters based on a vertically stacked-nanosheet (NS) structure were fabricated. The NS below 8-nm channel layer thickness ( ${T}_{{\text {Si}}}$ ) was obtained by dry etching and wet etching processes. The channel thickness is controlled by dry etching, and the channel width was shrunk down by wet etching. Compared to single nanowire field-effect transistors (NSFETs), stacked NSFETs exhibit higher ON-current performance. For the CMOS inverter, the voltage transfer characteristics (VTCs) could be matched much better by adjusting the channel widths and layers for N-channel MOSFET (NFET) and P-channel MOSFET (PFET), respectively. For the CFET inverter, layout areas could be reduced and requires less number of lithographic and ion implantation steps contrary to the CMOS inverter. However, we observe that the VTCs of the CFET inverters still show asymmetric behavior due to the difficulties of adjustment in NS layers and systematic behavior of threshold voltages for NFETs/PFETs. This work experimentally demonstrates the CMOS and CFET inverters on the vertically stacked NS structure, which is promising for system-on-panel (SoP) and 3-D-ICs applications.

Corrigendum to “Sensitivity of P-Channel MOSFET to X- and Gamma-Ray Irradiation”

Corrigendum to “Sensitivity of P-Channel MOSFET to X- and Gamma-Ray Irradiation”

Superjunction IGBT With Conductivity Modulation Actively Controlled by Two Separate Driving Signals

A dual-gate superjunction insulated gate bipolar transistor (IGBT) (DG-SJ-IGBT) is proposed and studied with numerical TCAD simulations. The new structure utilizes the superjunction structure as a controlling port for the strength of conductivity modulation inside the IGBT, so that a low ${V}_{\text {ON}}$ is obtained by a strong conductivity modulation during ON-state and a near-unipolar turn-off is achieved by removing the minority carriers before the turn-off event. For this purpose, the p-pillar in the DG-SJ-IGBT is connected to the p-body using a built-in p-channel MOSFET. The primary gate and the auxiliary gate (i.e., gate of p-MOSFET) are controlled by two separate driving signals. In the IGBT’s ON-state, the p-MOSFET disconnects the p-pillar, enabling full conductivity-modulated bipolar conduction and a consequent low ${V}_{\text {ON}}$ . As a well-known issue, conductivity modulation is accompanied by significant additional turn-off loss ( ${E}_{\text {OFF}}$ ). To overcome this issue, the DG-SJ-IGBT takes advantage of the p-pillar which extends through the entire drift region. Before the IGBT’s turn-off event, the p-MOSFET electrically grounds the p-pillar to the p-body. The grounded p-pillar serves as a hole extractor, suppresses the minority carrier density throughout the depth of the drift region, and brings the device into a near-unipolar conduction mode. Thus, a near-unipolar turn-off can be obtained, resulting in a low ${E}_{\text {OFF}}$ .

Improved electrical characteristics of Ge nMOSFET with suitable nitrogen content in starting interfacial layer

The realization of Ge n-channel MOSFETs (nMOSFET) encounters many challenges, such as poorer interface quality and thermal stability, in comparison with Ge p-channel MOSFETs. Since the oxygen vacancy and interface trap in gate dielectric can be effectively passivated by a nitrogen incorporation, a germanium oxynitride (GeON) starting interfacial layer with suitable nitrogen content was proposed to improve the interface quality of Ge nMOSFETs in this work. A low equivalent oxide thickness of ~0.6 nm, a low gate leakage current of ~6 × 10−4 A/cm2, and a low subthreshold swing of ~120 mV/dec in Ge nMOSFET can be simultaneously achieved by incorporating a nitrogen content of ~20.4% in the GeON starting interfacial layer.

Uniformity of Gate Dielectric for I/O and Core HK/MG pMOSFETs with Nitridation Treatments

Uniformity consideration in integrated-circuit manufacturing is an impressive task, especially in the field of nano-node semiconductors. The use of high-dielectric-constant (high-K) materials to promote drive current in deep nano-node devices is also increasing. One solution involves enhancing the quality of the high-K dielectric layer as a gate dielectric with nitridation treatment. This study combines the aforementioned concerns in deep nano-node manufacturing and demonstrates their relationship. Given the electrical measurement of the wafers treated with decoupled plasma nitridation (DPN), a few desired key parameters, including drive current (IDS), threshold voltage (Vth), gate oxide capacitance per area (Cox), subthreshold swing (SS), and interface state density, in the design of p-channel metal–oxide–semiconductor field-effect transistors (pMOSFETs) are observed. A uniformity comparison with different DPN processes is also performed, and the uniformity of the gate dielectric in input/output and core zones is discussed. Based on the uniformity distribution, lower SS values are obtained by adopting the low-temperature nitridation treatment after high-K dielectric deposition. The increased nitrogen concentration decreases the deviation, thereby indicating improved uniformity of SS values.

Significant reduction of interface trap density of SiC PMOSFETs by post-oxidation H2O annealing processes with different oxygen partial pressures

We investigated the effects of the post-oxidation annealing in H2O (wet-POA) with various conditions after dry oxidation for p-type 4H-SiC (0001) metal-oxide-semiconductor (MOS) capacitors and 4H-SiC (0001) p-channel MOS field-effect transistors (PMOSFETs). Interface state density, fixed charge density, and slow trap density in near-interface oxide were reduced by the wet-POA with additional growth of only <1 nm oxide at the interface. With those POAs the improved PMOSFET performance was also demonstrated. The degradation of flatband voltage (VFB) stability, which has been regarded as one of the serious drawbacks of wet oxidation of SiC, was efficiently suppressed by a careful selection of the wet-POA conditions with low O2 partial pressure at high temperature. Even though the reason why the VFB stability is so sensitive to the wet-POA condition is not clarified yet, these results give us a guideline to design wet-POA conditions appropriate for SiC PMOSFETs.