Voltage stress induced interface states and hole trapping in germanium pMOSFETs with high-k gate dielectric and metal-gate electrode

Abstract

In this work, p-channel MOSFETs with the metal-gate electrode and high-k gate stack of ZrO2/Al2O3/GeO2 on n-Ge substrate are fabricated and investigated. The interface state generation (ΔNit) and hole trapping (ΔNot) during voltage stresses are examined. According to the time dependence on the subthreshold swing and the threshold voltage, both ΔNit and ΔNot can be extracted during the gate voltage stresses, which is characterized by the power-low (tn) model. The time exponent of ΔNit is in the range of 0.48-0.65 which is approximately two times that of ΔNot. Based on the Si/oxide model, the charged H+ diffusion may be the dominant process in the degradation of interface states. In the early stressing, the device degradation of threshold voltage shift mainly results from the hole trapping in the gate dielectrics. However, the long-term trend indicates that ΔNot will be overwhelmed by ΔNit after a characteristic time (tc). This implies, for the device degradation during gate voltage stresses, the contribution of ΔNot decreases with time, meanwhile, the contribution of ΔNit increases with time. According to the experimental results, the characteristic time is approximately independent of stress voltage and is about 106 s.