Significant reduction of interface trap density of SiC PMOSFETs by post-oxidation H2O annealing processes with different oxygen partial pressures

Abstract

We investigated the effects of the post-oxidation annealing in H2O (wet-POA) with various conditions after dry oxidation for p-type 4H-SiC (0001) metal-oxide-semiconductor (MOS) capacitors and 4H-SiC (0001) p-channel MOS field-effect transistors (PMOSFETs). Interface state density, fixed charge density, and slow trap density in near-interface oxide were reduced by the wet-POA with additional growth of only <1 nm oxide at the interface. With those POAs the improved PMOSFET performance was also demonstrated. The degradation of flatband voltage (VFB) stability, which has been regarded as one of the serious drawbacks of wet oxidation of SiC, was efficiently suppressed by a careful selection of the wet-POA conditions with low O2 partial pressure at high temperature. Even though the reason why the VFB stability is so sensitive to the wet-POA condition is not clarified yet, these results give us a guideline to design wet-POA conditions appropriate for SiC PMOSFETs.