On-chip Interconnection Networks Research Articles

A comparative study of FPGA and CGRA technologies in hardware acceleration for deep learning

With the rapid growth of deep neural networks, their increasing demand for computing resources poses significant challenges to resource-constrained edge devices. Field Programmable Gate Array (FPGA) and Coarse-Grained Reconfigurable Arrays (CGRA) have emerged as promising solutions due to their parallelism and energy efficiency advantages. This paper conducts a comprehensive comparative analysis of FPGA and CGRA for accelerating deep learning workloads. It begins by introducing convolutional neural network architecture and optimization techniques. Various dataflow strategies are discussed for memory access optimization. The paper then analyzes representative cases to clarify FPGA and CGRA architectural advantages, along with optimization techniques through different dataflow strategies. The comparison reveals that FPGA offers higher throughput with fine-grained programmability for flexible bit-level operations and dataflow control. In contrast, CGRA excels in energy efficiency and area consumption with coarse-grained custom processing units and optimized on-chip interconnection networks. Quantitative comparisons are provided for throughput, energy efficiency, and area occupation. These insights can serve as a reference for selecting the appropriate architecture when designing custom hardware accelerators for deep learning workloads.

Comparative analysis of 2D mesh topologies with additional communication links for on-chip networks

Multiprocessor system-on-chip (MPSoC) is playing a vital role in recent embedded technologies. One of the main challenges of this system is its communication bottleneck which limits performance scaling capabilities. In order to overcome this restriction, on-chip interconnection networks have been proposed. Several topologies have been suggested in the literature, but the most popular one remains the mesh topology due to its systematic and scalable design structure. Although, the functionality and performance of network-based mesh topologies degrade significantly with growing system size, which results in the network diameter and the dependency on small bisection width. A wide range of modified designs has been proposed in the literature with various types of additional links to improve the network performance. However, these links result in additional cost overhead on the system in terms of area, energy, and power consumption. Among the selected competitor meshes, it is observed that the link design of d-Torus produces high performance at elevated communication costs. The design of the CBP-Torus is less complex and results in lower communication costs compared to d-Torus with similar performance. The selection of an appropriate mesh-type topology of the target application is, therefore, a tradeoff between the performance and cost of the network. This paper analyzes the impact of additional links on the performance of on-chip mesh architectures. The comparative analysis includes performance characteristics, structural complexity, power consumption, and area utilization. This research work provides a roadmap for the designers to choose the most appropriate topology for a particular design.

Detection and Localization of Channel-Short Faults in Regular On-Chip Interconnection Networks

Detection and Localization of Channel-Short Faults in Regular On-Chip Interconnection Networks

A Framework for Design, Verification, and Management of SoC Access Control Systems

System-on-chip (SoC) architectures are a heterogeneous mix of microprocessors, custom accelerators, memories, interfaces, peripherals, and other resources. These resources communicate using complex on-chip interconnect networks that attempt to quickly and efficiently arbitrate memory transactions whose behaviors can vary drastically depending on the current mode of operation and system operating state. Security- and safety-critical applications require access control policies that define how these resources interact to ensure that malicious and unsafe behaviors do not occur. <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Aker</small> is a design and verification framework for on-chip access control. The core of <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Aker</small> is the access control wrapper (ACW)–a high-performance yet efficient hardware module that dynamically arbitrates on-chip communications. <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Aker</small> distributes ACWs across the SoC and programs them to perform local access control. <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Aker</small> provides a firmware generation tool and a property-driven security verification methodology to ensure that the ACWs are properly integrated and configured. <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Aker</small> security verification confirms that the ACW behaves properly at IP level. It verifies the hardware root of trust firmware configures the ACW correctly. And it evaluates system-level security threats due to interactions between shared resources. <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Aker</small> is experimentally validated on a Xilinx UltraScale+ programmable SoC. Additionally, an <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Aker</small> access control system is integrated into the OpenPULP multicore archtiecture that uses OpenTitan hardware root-of-trust for firmware configuration.

3D layout of the Spidergon-Donut on-chip interconnection network

3D layout of the Spidergon-Donut on-chip interconnection network

JARVA: Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation

This article proposes a joint application-aware oblivious routing and static virtual channel allocation framework to enable better deadlock-free performance in on-chip interconnection networks.

Design and evaluation of an energy efficient DiamondMesh topology for on-chip interconnection networks

Design and evaluation of an energy efficient DiamondMesh topology for on-chip interconnection networks

A Novel Hybrid Hexagonal Star Topology for On-Chip Interconnection Networks

Network-on-Chip (NoC) is an emerging and efficient on-chip interconnection network. NoC is expected to be the communication backbone of next-generation Multi-processor System-on-Chip (MPSoC) architectures. Topology is a crucial design aspect of NoC, as it affects the performance of the interconnection network. This paper proposes a novel, scalable, hybrid Hexagonal Star (HS) topology for on-chip interconnection networks. Properties of the proposed topology have been explored and compared with those of Mesh, Torus and Honeycomb Mesh topologies. The performance of the Hexagonal Star topology has been evaluated and compared with that of Mesh topology for different scenarios. The comparative studies of topological properties have indicated that the proposed topology can be a potential choice for on-chip interconnection networks. The simulation results have shown that the proposed topology outperforms Mesh topology in terms of latency for low traffic loads. For different traffic patterns and traffic loads, HS topology has registered a reduction of packet latency ranging from 15% to 50% and from 9% to 23% for 18 nodes and 32 nodes, respectively, compared to Mesh topology.

Design and implementation of congestion aware router for network-on-chip

Network-on-Chip (NoC) is the state of the art on-chip interconnection network for packet based communication. NoCs can offer low packet latency, high bandwidth, high throughput with minimum area, better energy efficiency and fault tolerance. Routers are the basic building blocks of the NoCs. In this paper, we present the design of a Congestion Aware Router for NoC which is then implemented using Vivado HLS. The router is then used to develop a scalable NoC based on mesh topology. Using the NoC as a test bed we carry out simulations and estimate performance metrics like latency, waiting time and total packets handled for various configurations of NoC. Provisions to alter parameters like buffer depth, packet size, packet injection interval and traffic are also added. Further, we propose a simple mechanism for detecting congestion at the router. The congestion metric is then used to adapt the XY dimension order routing into a Congestion Aware minimal adaptive X/Y routing strategy with very low hardware overhead. The proposed routing method is compared against conventional XY DOR, GCA routing and RCS based routing algorithms for different parameter variations. The results show that the proposed routing method can reduce packet latency for different traffic patterns at medium packet injection rates.

Knowledge-Based Neural Networks for Fast Design Space Exploration of Hybrid Copper-Graphene On-Chip Interconnect Networks

In this article, an artificial neural network (ANN) is developed in order to predict the per-unit-length (p. u. l.) parameters of hybrid copper-graphene on-chip interconnects from a prior knowledge of their structural geometry and layout. The salient feature of the proposed ANN is that it combines knowledge of the p. u. l. parameters extracted from empirical models along with that extracted from a rigorous full-wave electromagnetic solver. As a result, the proposed ANN is referred to as a knowledge-based neural network (KBNN). The KBNN has been found to converge to the same accuracy as a conventional ANN but at the expense of far smaller training time costs. As a result, the KBNN is much more suitable for performing design space explorations.

Design and Simulation of Ring Network-on-Chip for Different Configured Nodes

The network-on-chip (NoC) technology is frequently referred to as a front-end solution to a back-end problem. The physical substructure that transfers data on the chip and ensures the quality of service begins to collapse when the size of semiconductor transistor dimensions shrinks and growing numbers of intellectual property (IP) blocks working together are integrated into a chip. The system on chip (SoC) architecture of today is so complex that not utilizing the crossbar and traditional hierarchical bus architecture. NoC connectivity reduces the amount of hardware required for routing and functions, allowing SoCs with NoC interconnect fabrics to operate at higher frequencies. Ring (Octagons) is a direct NoC that is specifically used to solve the scalability problem by expanding each node in the shape of an octagon. This paper discusses the ring NoC design concept and its simulation in Xilinx ISE 14.7, as well as the communication of functional nodes. For the field-programmable gate array (FPGA) synthesis, the performance of NoC is evaluated in terms of hardware and timing parameters. The design allows 64 to 256 node communication in a single chip with ‘N’ bit data transfer in the ring NoC. The performance of the NoC is evaluated with variable nodes from 2 to 256 in Digilent manufactured Virtex-5 FPGA hardware.

Transient analysis of graphene-based on-chip interconnects using closed-form MRA model

As interconnects in very-large-scale-integration technology shrinks into the sub-22 nm regime, carbon nanotubes, graphene nanoribbons (GNRs), and Cu-GNRs are emerging as potential replacements for conventional copper on-chip interconnects. This paper presents an matrix-rational-approximation (MRA) model for the fast transient analysis of graphene-based on-chip interconnects. The proposed model’s key feature is that it allows the mathematical representation of the transfer function matrix of on-chip graphene-based interconnect networks in the frequency-domain using closed-form rational functions. The network’s rational functions coefficients are derived from per-unit-length parameters and predetermined coefficients of the Padé approximation. The graphene-based network’s time-domain model is directly obtained from the rational function frequency-domain model without any numerical integration techniques. This makes the proposed MRA model more numerically efficient than conventional simulation program with integrated circuit emphasis (SPICE) models. The results obtained using the proposed model show less than 1% error when compared with HSPICE simulations, ensuring the proposed model’s excellent accuracy. A wide eye-height of 0.8137 V and eye-width of 219.87 ps are obtained for the eye-diagram analysis of multilayer graphene nanoribbon lines at 4 Gbps.

Silicon reconfigurable mode-selective modulation for on-chip mode-multiplexed photonic systems.

Recently, optical mode-division multiplexing has drawn a lot of attention due to its ability to increase the optical communication capacity in one physical channel with a single wavelength carrier. In this Letter, we demonstrate reconfigurable mode-selective modulation which is potentially useful for on-chip mode-multiplexed photonic systems. The device consists of two mode exchangers and one TE1 mode modulator. The mode exchanger is based on a Mach-Zehnder interferometer that performs mode exchange between TE0 and TE1 modes. The TE1 mode modulator consists of a pair of 1×3/3×1 multimode interferometers acting as a mode (de)multiplexer. It only selectively modulates the TE1 mode while bypassing the TE0 mode. 32 Gb/s on-off keying (OOK) modulation is successfully demonstrated for both input TE0 and TE1 modes. This device can be used as a building block for on-chip multimode interconnect networks.

A Temperature and Dielectric Roughness-Aware Matrix Rational Approximation Model for the Reliability Assessment of Copper– Graphene Hybrid On-Chip Interconnects

In this article, a closed-form matrix rational approximation (MRA) model is presented for the reliability assessment of copper–graphene hybrid on-chip interconnect networks. The key feature of this MRA model is its capacity to predict how the different values of temperature and dielectric roughness affect the signal integrity performance of the hybrid interconnect networks. As a result, the proposed MRA model is well suited for very fast parametric sweeps and worst case analysis of the hybrid interconnect networks, which has not been possible using existing closed-form models or even SPICE simulations. Numerical examples show that the proposed model is significantly more efficient than conventional models while exhibiting error less than 5%.

Reconfigurable Network-on-Chip Security Architecture

Growth of the Internet-of-things has led to complex system-on-chips (SoCs) being used in the edge devices in IoT applications. The increased complexity is demanding designers to consider several critical factors, such as dynamic requirement changes, long application life, mass production, and tight time-to-market deadlines. These requirements lead to more complex security concerns. SoC manufacturers outsource some of the intellectual property cores integrated on the SoC to untrusted third-party vendors. The untrusted intellectual properties can contain malicious implants, which can launch attacks using the resources provided by the on-chip interconnection network, commonly known as the network-on-chip (NoC). Existing efforts on securing NoC have considered lightweight encryption, authentication, and other attack detection mechanisms such as denial-of-service and buffer overflows. Unfortunately, these approaches focus on designing statically optimized security solutions. As a result, they are not suitable for many IoT systems with long application life and dynamic requirement changes. There is a critical need to design reconfigurable security architectures that can be dynamically tuned based on changing requirements. In this article, we propose a tier-based reconfigurable security architecture that can adapt to different use-case scenarios. We explore how to design an efficient reconfigurable architecture that can support three popular NoC security mechanisms (encryption, authentication, and denial-of-service attack detection and localization) and implement suitable dynamic reconfiguration techniques. We evaluate our proposed framework by running standard benchmarks enabling different tiers of security and provide a comprehensive analysis of how different levels of security can affect application performance, energy efficiency, and area overhead.

A Routing-Aware Simulated Annealing-based Placement Method in Wireless Network on Chips

Wireless network on chip (WiNoC) is one of the promising on-chip interconnection networks for on-chip system architectures. In addition to wired links, these architectures also use wireless links. Using these wireless links makes packets reach destination nodes faster and with less power consumption. These wireless links are provided by wireless interfaces in wireless routers. The WiNoC architectures differ in the position of the wireless routers and how they interact with other routers. So, the placement of wireless interfaces is an important step in designing WiNoC architectures. In this paper, we propose a simulated annealing (SA) placement method which considers the routing algorithm as a factor in designing cost function. To evaluate the proposed method, the Noxim, which is a cycle-accurate network-on-chip simulator, is used. The simulation results show that the proposed method can reduce flit latency by up to 24.6% with about a 0.2% increase in power consumption.

Fast Physics-Based Electromigration Analysis for Full-Chip Networks by Efficient Eigenfunction-Based Solution

Electromigration (EM) becomes one of the most challenging reliability issues for current and future ICs in 10-nm technology and below. In this article, a novel method is proposed for the EM hydrostatic stress analysis on 2-D multibranch interconnect trees, which is the foundation of the EM reliability assessment for large-scale on-chip interconnect networks, such as on-chip power grid networks. The proposed method, which is based on an eigenfunction technique, could efficiently calculate the hydrostatic stress evolution for multibranch interconnect trees stressed with different current densities and nonuniformly distributed thermal effects. The proposed method solves the partial differential equations of transient EM stress more efficiently since it does not require any discretization either spatially or temporally, which is in contrast to numerical methods, such as the finite difference method and finite element method. The accuracy of the proposed transient analysis approach is validated against the analytical solution and commercial tools. The convergence of the proposed method is demonstrated by numerical experiments on practical power/ground networks, showing that only a small number of eigenfunction terms are necessary for the accurate solution. Thanks to its analytical nature, the proposed method is also utilized in efficient EM analysis techniques, such as searching for the void nucleation time by a modified bisection algorithm. The numerical results show that the proposed method is 10X–100X faster than the finite difference method and scales better for larger interconnect trees.

A survey and taxonomy of congestion control mechanisms in wireless network on chip

Wireless network on chip (WiNoC) has been proposed as a promising solution for on-chip interconnection network due to high scalability, high bandwidth, and low latency. However, the variations of traffic pattern distribution and data flow lead to congestion in wireless interfaces-equipped routers (WRs). Congestion is one of the main challenges in emerging WiNoCs that can reduce network performance. In recent years, various researches have been proposed to decrease congestion in WiNoCs. However, this paper presents a comprehensive survey of the significant congestion control mechanisms in WiNoCs. The available schemes are classified into six categories, includeing hardware resources-based congestion control, congestion-aware routing algorithms, medium access control protocol,congestion-aware architectures, rate-based congestion control, and application-mapping with task-migration techniques. The goal of this survey is to highlight the characteristics and inherent constraints of congestion control mechanisms in a novel approach that can help researchers for designing efficient congestion control scheme.

Reconfigurable on-chip interconnection networks for high performance embedded SoC design

Abstract System on Chip (SoC) based embedded devices are providing key solutions to meet the demands of current and future high-performance embedded applications. These solutions become critical when the SoC IC designs are affected by the limitation of sub nanometer technologies that cannot be shrunk further. Network on Chip (NoC) is a scalable communication system that can provide efficient solutions for on-chip interconnection problems of SoCs such as re-configurability for multiple embedded applications. Most of the reconfigurable NoCs presented in the past improve performance of SoC at the expense of higher power and additional hardware. In this paper, we present a novel high-performance re-configurable NoC architecture that can improve the performance along with similar or improved power requirements of the system for different SoC applications. The proposed NoC architecture can also be considered as a hard IP for future partially configurable FPGA devices. Simulation and experimental results of our approach are compared with the recent on-chip interconnection approaches that supports our claim.

Efficient Support of AXI4 Transaction Ordering Requirements in Many-Core Architecture

The Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface 4 (AXI4) protocol was initially a bus oriented interface designed for on-chip communication. To offer the possibility of utilizing the AXI4 based processors and peripherals in the on-chip network based system, we propose a whole system architecture solution to make the AXI4 protocol compatible with the Network-on-Chip (NoC) based communication interconnect in the many-core architecture. Due to the out-of-order transaction in the NoC interconnect, which conflicts with the ordering requirements specified by the AXI4 protocol, we especially focus on the design of the transaction ordering units, realizing a high-performance and low cost (area) solution to the ordering requirements by the sequence ID (seq_ID) reuse mechanism and a simple but smart seq_ID synchronization process. Besides, the micro-architectures and the functionalities of the transaction ordering units are described and explained in detail for ease of implementation. The experimental results in a C++ based system simulator show that, compared with the state-of-the-art works, our solution can maximally increase the system throughput by 66.0% and decrease the transaction queueing delay in the master-side ordering unit by 91.2%.