Reconfigurable on-chip interconnection networks for high performance embedded SoC design

Abstract

Abstract System on Chip (SoC) based embedded devices are providing key solutions to meet the demands of current and future high-performance embedded applications. These solutions become critical when the SoC IC designs are affected by the limitation of sub nanometer technologies that cannot be shrunk further. Network on Chip (NoC) is a scalable communication system that can provide efficient solutions for on-chip interconnection problems of SoCs such as re-configurability for multiple embedded applications. Most of the reconfigurable NoCs presented in the past improve performance of SoC at the expense of higher power and additional hardware. In this paper, we present a novel high-performance re-configurable NoC architecture that can improve the performance along with similar or improved power requirements of the system for different SoC applications. The proposed NoC architecture can also be considered as a hard IP for future partially configurable FPGA devices. Simulation and experimental results of our approach are compared with the recent on-chip interconnection approaches that supports our claim.