Design and implementation of congestion aware router for network-on-chip

Abstract

Network-on-Chip (NoC) is the state of the art on-chip interconnection network for packet based communication. NoCs can offer low packet latency, high bandwidth, high throughput with minimum area, better energy efficiency and fault tolerance. Routers are the basic building blocks of the NoCs. In this paper, we present the design of a Congestion Aware Router for NoC which is then implemented using Vivado HLS. The router is then used to develop a scalable NoC based on mesh topology. Using the NoC as a test bed we carry out simulations and estimate performance metrics like latency, waiting time and total packets handled for various configurations of NoC. Provisions to alter parameters like buffer depth, packet size, packet injection interval and traffic are also added. Further, we propose a simple mechanism for detecting congestion at the router. The congestion metric is then used to adapt the XY dimension order routing into a Congestion Aware minimal adaptive X/Y routing strategy with very low hardware overhead. The proposed routing method is compared against conventional XY DOR, GCA routing and RCS based routing algorithms for different parameter variations. The results show that the proposed routing method can reduce packet latency for different traffic patterns at medium packet injection rates.