Comparative analysis of 2D mesh topologies with additional communication links for on-chip networks

Abstract

Multiprocessor system-on-chip (MPSoC) is playing a vital role in recent embedded technologies. One of the main challenges of this system is its communication bottleneck which limits performance scaling capabilities. In order to overcome this restriction, on-chip interconnection networks have been proposed. Several topologies have been suggested in the literature, but the most popular one remains the mesh topology due to its systematic and scalable design structure. Although, the functionality and performance of network-based mesh topologies degrade significantly with growing system size, which results in the network diameter and the dependency on small bisection width. A wide range of modified designs has been proposed in the literature with various types of additional links to improve the network performance. However, these links result in additional cost overhead on the system in terms of area, energy, and power consumption. Among the selected competitor meshes, it is observed that the link design of d-Torus produces high performance at elevated communication costs. The design of the CBP-Torus is less complex and results in lower communication costs compared to d-Torus with similar performance. The selection of an appropriate mesh-type topology of the target application is, therefore, a tradeoff between the performance and cost of the network. This paper analyzes the impact of additional links on the performance of on-chip mesh architectures. The comparative analysis includes performance characteristics, structural complexity, power consumption, and area utilization. This research work provides a roadmap for the designers to choose the most appropriate topology for a particular design.