Networks-on-chip emulator design with FPGA array

Abstract

As the Multi-Processors System on Chip(MPSoC) platforms are becoming increasingly more heterogeneous and shifting towards a more communication-centric methodology, the networks on chip(NoC) has emerged as the design paradigm for scalable on-chip communication architecture. How to design and verify such a NoC-based MPSoC platform in a systematic and automatic way becomes an interesting issue for NoC study. In this paper we present a NoC verification platform with a FPGA array which contains 16 micro-processors to perform Intellectual Property (IP) functions. A novel configurable network interface is proposed as user-defined IP attached to processor. To reduce the area and power consumption, Virtual Output Queue (VOQ) wormhole switch architecture is used in this verification platform. The network which employs a 4 × 4 mesh topology, full duplex communication, distributed routing algorithm, and wormhole routing mechanism is adopted on the verification platform. An OFDM transceiver is mapped on the verification platform. The whole design occupies only 50% of entire area in terms of slices and provides 51.2Mbps aggregated bandwidth. The experiment shows that NoC frameworks can be verified on our FPGA array platform.