Efficient Support of AXI4 Transaction Ordering Requirements in Many-Core Architecture

Boqian Wang,Zhonghai Lu

doi:10.1109/access.2020.3029014

Abstract

The Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface 4 (AXI4) protocol was initially a bus oriented interface designed for on-chip communication. To offer the possibility of utilizing the AXI4 based processors and peripherals in the on-chip network based system, we propose a whole system architecture solution to make the AXI4 protocol compatible with the Network-on-Chip (NoC) based communication interconnect in the many-core architecture. Due to the out-of-order transaction in the NoC interconnect, which conflicts with the ordering requirements specified by the AXI4 protocol, we especially focus on the design of the transaction ordering units, realizing a high-performance and low cost (area) solution to the ordering requirements by the sequence ID (seq_ID) reuse mechanism and a simple but smart seq_ID synchronization process. Besides, the micro-architectures and the functionalities of the transaction ordering units are described and explained in detail for ease of implementation. The experimental results in a C++ based system simulator show that, compared with the state-of-the-art works, our solution can maximally increase the system throughput by 66.0% and decrease the transaction queueing delay in the master-side ordering unit by 91.2%.

Highlights

Advanced eXtensible Interface 4 (AXI4) is the fourth generation of the Advanced Microcontroller Bus Architecture (AMBA) interface specification from ARM [1]
We propose a high-performance AXI4 transaction ordering solution for the ordering units in the network interface (NI) by supporting sequence ID (seq_ID) reuse mechanism (Section IV-B), which compared with the state-of-theart designs, can greatly increase the whole system throughput and decrease the transaction’s transfer delay
We show and explain the synchronization behavior among the transaction ordering units, which can ensure the correctness of ordering process and simplify the hardware structure of the transaction ordering units

Summary

INTRODUCTION

Advanced eXtensible Interface 4 (AXI4) is the fourth generation of the Advanced Microcontroller Bus Architecture (AMBA) interface specification from ARM [1]. We propose a high-performance AXI4 transaction ordering solution for the ordering units in the network interface (NI) by supporting seq_ID reuse mechanism (Section IV-B), which compared with the state-of-theart designs, can greatly increase the whole system throughput and decrease the transaction’s transfer delay. They utilize distributed arbitration to decrease the read delay due to out-of-order data arrivals when dynamic reordering memory read accesses the reorder buffer All these works consider the transaction ordering problem in a quite general scenario, which can not be directly utilized to support the ordering requirement specified by the AXI4 protocol. They utilize a sequence ID to record the sequence of a series of transactions, which will be referred to in the NI for the reordering purpose

BACKGROUND

MASTER-SIDE ORDERING UNIT

SLAVE-SIDE ORDERING UNIT

EXPERIMENTAL RESULTS

Findings

CONCLUSION