On-chip Compensation Research Articles

A Fast-Transient Responses Power-efficiency LDO Regulator with Transient-current Enhanced Buffer

In this paper, we introduce a Low-Dropout (LDO) Regulator that features a transient-current enhanced buffer, providing fast transient responses and high-power efficiency. The buffer, which incorporates an AC-coupled network and a high-gain stage, enhances the load transient response by boosting the charging or discharging current to the gate capacitor of the power transistor, without consuming extra power under varying load conditions. The LDO was designed using a standard 65 nm CMOS process and has a load capacitance of 100 pF and an on-chip compensation capacitance of only 2.7 pF. Simulation results reveal that the LDO has a low static current of 20 μA and a maximum load capacity of 200 mA. When the LDO output switches from a light load of 100 μA to a heavy load of 20 mA within 1 μs, the undershoot voltage is 53 mV and the transient response time is 1.34 μs. Conversely, when switching from heavy load to light load, the overshoot voltage is 51 mV and the transient response time is 0.50 μs.

A feed-forward compensated FVF LDO regulator with no on-chip compensation capacitors

This paper proposes a capacitor-free Flipped Voltage Follower (FVF) Low Dropout (LDO) regulator. To stabilize the feed-back loop, the proposed multi-stage FVF LDO regulator does not require a Miller compensation capacitor or physical resistor. A capacitor-free internal structure improves closed-loop bandwidth while saving area in the LDO regulator. In this work, a large feed-forward transconductor (gmf) is proposed, which generates a strong left-half-plane (LHP) zero while consuming a small bias current. The large feed-forward transconductor boosts the LDO regulator’s DC gain and bandwidth. The proposed FVF LDO regulator is implemented in standard 130nm CMOS technology and achieves a unity gain frequency of more than 35 MHz while consuming a total quiescent current of 97μA. The proposed FVF LDO regulator has an active area of 0.0054mm2, which is less than many other LDO regulators that have been reported.

An LDO Circuit Design Based On On-chip Compensation

This paper proposes a liner low-dropout regulator (LDO) circuit using on-chip steady-state compensation technology. Firstly, a bandgap reference is designed with low temperature drift and low power consumption. Secondly, the on-chip compensation is adopted in the LDO, which can avoid the use of large off-chip capacitors and reduce the layout area of the LDO circuit. The circuit performances are verified in the TSMC 180 nm CMOS process. Test results show that temperature coefficient of the bandgap reference circuit is as low as 4.3 × 10-6 °C in the temperature range of -40°C to 125°C. The static current under the 3V power supply voltage is 4 μA. The LDO output voltage Vout is 1.8V . And the core area of the chip is 0.0848 mm2.

A 5 V-to-32 V Input PVT-Robust Charge-Pump Circuit with Adjustable Output in a 0.18 μm BCD Process

In this paper, a new closed-loop charge-pump circuit with adjustable output voltage and an on-chip compensation technique is proposed. The environmental temperature and process corner can be detected with an on-chip detection circuit and automatically feedback an adjusted reference voltage. With this, the magnitude of the charge-pump output voltage with Pulse-Width Modulation (PWM) can be compensated. The charge-pump circuit is designed and verified with a 180 nm Bipolar-CMOS-DMOS (BCD) process, and its output voltage at different process, voltage, and temperature (PVT) is controllable with low ripple. There are three selections for adjusting the output voltage: +5 V/+7 V/+10 V shifts, with the supply voltage ranging from 5 V to 32 V. It can remain tunable and stable at any shifts. The maximum deviation is ±0.265%, and the maximum load current can reach 30 mA. The ripple voltage is less than 0.3% (Δ Vripple/Vout) underthe maximum load. The Monte Carlo simulation results show that the worst case of the process sensitivity (σ/μ) is 0.1%. The charge-pump core area is 0.308 mm2, and the power consumption is 4.753 mW. The circuit can produce high-precision output and is suitable for high-side driving IC applications.

Digital domain dynamic path accumulation method to compensate for image vibration distortion for CMOS-time-delay-integration image sensor

A digital domain dynamic path accumulation method for a time-delay-integration (TDI) image sensor that can realize on-chip compensation for image distortion caused by sensor vibration is proposed. Through the proposed method, the exposure signals are controlled to enter the corresponding accumulator according to the vibration vector, ensuring the synchronous accumulation of different stages of pixels on the same object. The behavior level model of the method is established. The structural similarity (SSIM) between images without distortion, distorted images, and images compensated for by the proposed method is simulated and analyzed to verify the effectiveness of the method. Compared with conventional TDI, the SSIM between images with and without vibration is improved from 0.2322 to 0.9858, as the vibration level is 1 pixel per stage. With fixed TDI stages and the vibration level varying from 0 to 2 pixels per stage, the SSIM of conventional TDI drops rapidly to about 0.2 while that of the dynamic path accumulation method maintains at about 0.95. The proposed method is suitable for an antivibration CMOS-TDI image sensor of remote imaging systems.

Dual Active-Feedback Frequency Compensation for Output-Capacitorless LDO With Transient and Stability Enhancement in 65-nm CMOS

An output-capacitorless low-dropout regulator (OCL-LDO) using a dual-active feedback frequency compensation (DAFFC) scheme with both transient and stability enhancement has been presented in this paper. The DAFFC scheme consists of two parallel active feedback paths, which creates two pole-zero pairs to effectively enhance the stability and transient response for the proposed OCL-LDO. Compared to the conventional single-path active-feedback frequency compensation method, the proposed DAFFC technique has provided one more design freedom with one more active feedback loop deployed and has been proved to be capable of obtaining better compensation effects with the same capacitor budget. Besides, the induced extra ac currents by the two active feedback loops have also enhanced the transient response of the proposed OCL-LDO. To substantiate the proposed DAFFC, a telescopic cascode output stage for error amplifier, and two on-chip compensation capacitors (5 and 1 pF, respectively) are needed. The proposed OCL-LDO has been implemented in 65-nm CMOS technology and the active chip area is 0.0105 mm2. The output voltage is 0.8 V, and the minimum input voltage is 0.95 V at 100-mA loading current. The proposed OCL-LDO can work stably in a load range of 0 to 100 mA with 14-μA quiescent current.

Theoretical Analysis and Experimental Verification on High-Isolation Surface-Acoustic-Wave Duplexer with On-Chip Compensation Circuit

Theoretical Analysis and Experimental Verification on High-Isolation Surface-Acoustic-Wave Duplexer with On-Chip Compensation Circuit

High-Isolation SAW Duplexer With On-Chip SAW Compensation Circuit Optimized for Isolated Multiple Frequency Bands.

This article describes the simulation analysis and experimental verification of a new type of high-isolation surface-acoustic wave (SAW) duplexer by using an SAW on-chip compensation circuit designed to cancel the leakage signal of the main SAW duplexer at multiple frequency bands. First, an analysis of amplitude and phase change of the SAW duplexer consists of a ladder-type transmitter (Tx) filter, and the double-mode SAW (DMS) receiver (Rx) filter is applied to clarify the cancellation conditions. Then, the feasibility of the SAW compensation circuit using a three-interdigital transducer (IDT) DMS resonator specially designed to satisfy the cancellation conditions is studied in circuit simulation based on the coupling-of-mode (COM) theory. Finally, we analyzed this concept in detail for a long-term-evolution (LTE) Band-I SAW duplexer for Tx and Rx band isolation in both a circuit simulation and experiment. Results showed that around 10-dB improvement of isolation in both the Tx and Rx bands was obtained without sacrificing other properties (e.g., insertion loss and attenuation) and that it agrees well with the result obtained by simulation analysis. These results are expected to be useful for now, considering that future mobile systems demand higher Rx sensitivity in multiple frequency bands.

An Analog-Front ROIC with On-Chip Non-Uniformity Compensation for Diode-Based Infrared Image Sensors.

This paper proposes a CMOS front-end readout-integrated circuit (ROIC) with on-chip non-uniformity compensation technique for a diode-based uncooled infrared image sensor. Two techniques are adopted to achieve on-chip non-uniformity compensation: a reference dummy metal line is introduced to alleviate the dominant non-uniformity with IR-drop presented in large pixel array, and a current splitting architecture-based variable current source for diode bias is proposed to compensate other residual non-uniformity. A differential integrator is chosen as the main amplifier of readout circuit for its superior noise performance. For low power design, a pulse-powered row buffer is designed in this work. The proposed ROIC for 384 × 288 diode-based detector array is fabricated with a 0.35-m CMOS process. It occupies an area of 4.4 mm × 15 mm, and the power consumption is 180 mW. The measured result shows that with the proposed on-chip non-uniformity compensation, the output voltage variation is greatly reduced from 2.5 V to 60 mV.

A Current-Mode Buck Converter With Reconfigurable On-Chip Compensation and Adaptive Voltage Positioning

Power management integrated circuits (PMICs) with on-chip compensation are widely used to power multiple loads in mobile devices with increased power density. However, there are two issues for on-chip compensated PMICs. First, on-chip compensation reconfigurability is required to obtain the appropriate response in various passive components. Second, a converter for a processor requires adaptive voltage positioning (AVP) to reduce the output capacitor size. In this paper, a novel reconfigurable on-chip compensated current-mode buck converter with AVP is proposed to solve the aforementioned issues without requiring high-speed and high-resolution analog-to-digital converter (ADC). A reconfigurable accurate load line control scheme and on-chip compensation are proposed to achieve an accurate load line and AVP in various load lines and passive components. The control scheme, small-signal model, and circuit implementation are illustrated in this paper. The proposed buck converter was implemented into an integrated circuit to verify the analysis.

Capacitor-Less Low-Dropout (LDO) Regulator With 99.99% Current Efficiency Using Active Feedforward and Reverse Nested Miller Compensations

In this paper, an output capacitor-less low-dropout (LDO) regulator with 99.99% current efficiency using active feedforward compensation (AFFC) and reverse nested Miller compensation (RNMC) is implemented. To increase the current efficiency, low quiescent current less than 10 μA is used. The stability problem arising from the low bias current is overcome by applying two kinds of compensation methods. By drawing the pole-zero plot using the open-loop transfer function obtained by the small-signal modeling, the stability of the proposed LDO is guaranteed to be less than 70 mA. By using the proposed compensation methods, two zeros of the right-half plane (RHP) can be placed in the left-half plane (LHP) to prevent lagging and reduce the on-chip compensation capacitor. The current efficiency of the proposed LDO is 99.99% at the load current of 70 mA.

Fast-transient capacitor-less low-dropout regulator with input current-differencing and dynamic current-boosting

Transient response improvement of a capacitor-less low-dropout regulator with input current-differencing is presented in this paper. The Miller compensation technique with series resistance is used to establish the stability and reduce the on-chip capacitor. As a result, the on-chip compensation capacitor of the proposed LDO is reduced to 4 pF which makes it suitable for portable SoC applications. The dynamic current-boosting technique is simultaneously applied to both the input current and the gate of the pass transistor to improve the line and load transient responses of the proposed LDO. The output voltage is regulated at 1 V with a dropout voltage of about 100 mV. The proposed circuit is simulated in TSMC 0.18 μm CMOS technology and its quiescent current is 42 μA. The simulation results of both the line and load transient responses show considerable improvement in the over/undershoot and the settling time of the proposed LDO as well as better transient performance compared to the similar previous works. The output voltage over/undershoot amplitudes of the proposed LDO are obtained 46/100 mV with the settling time of less than 2 μs for the load current changes from 0.1 to 100 mA with 1 µs rise/fall times.

A Fast-Transient Output Capacitor-Less Low-Dropout Regulator Using Active-Feedback and Current-Reuse Feedforward Compensation

In this paper, output capacitor-less low-dropout (LDO) regulator using active-feedback and current-reuse feedforward compensation (AFCFC) is presented. The open-loop transfer function was obtained using small-signal modeling. The stability of the proposed LDO was analyzed using pole-zero plots, and it was confirmed by simulations that the stability was ensured under the load current of 50 mA. The proposed compensation method increases gain-bandwidth product (GBW) and reduces the on-chip compensation capacitor. The proposed AFCFC technique was applied to a three-stage output capacitor-less LDO. The LDO has a GBW of 5.6 MHz with a small on-chip capacitor of 2.6 pF. Fast-transient time of 450 ns with low quiescent current of 65.8 μA was achieved. The LDO was fabricated in 130 nm CMOS process consuming 180 × 140 μm2 of the silicon area.

Output capacitor-free low-dropout regulator with fast transient response and ultra small compensation capacitor

A output capacitor-free low-dropout regulator (LDO) with fast transient response and ultra-small compensation capacitor is proposed. The slew-rate enhancement (SRE) circuit based on dynamic biasing technique is designed to improve load transient response for 100mA load step. The SRE circuit structure does not use any passive element to save silicon area and cost. The total active area of the proposed LDO is 0.043mm2 with 0.4pF on-chip compensation capacitor and the stability analysis is also included. The proposed LDO is implemented in 0.35µm process and experimental results show that it regulates the output voltage at 1.8V and 1V with dropout voltage of 200mV, 100mA maximum output-load current. The measured quiescent current is 15 μA only. For a 2V input voltage, the proposed LDO is able to regulate output voltage of 1.8V within 2μs with less than 148mV overshoot and undershoot. For a 1.2V input voltage, the LDO is able to regulate output voltage of 1V within 3μs with less than 152mV overshoot and undershoot.

A Two-Stage Large-Capacitive-Load Amplifier With Multiple Cross-Coupled Small-Gain Stages

A two-stage large-capacitive-load amplifier with multiple cross-coupled small-gain stages is proposed in this paper. The cross-coupled structure of the small-gain stages augments the large-signal responses, providing significant improvement in the effective output-stage transconductance and, hence, the gain–bandwidth product (GBW). Implemented in a standard 0.13- $\mu \text{m}$ CMOS technology and powered by a 0.7 V supply with a current consumption of $20~\mu \text{A}$ , the proposed amplifier achieves the GBW of 1.17 MHz and the phase margin of 74.8° while driving a capacitive load of 9.5 nF. The average slew rate is 0.3679 V/ $\mu \text{s}$ . The on-chip compensation capacitor is only 1.62 pF. The active chip area is 0.0056 mm2.

Monolithic semiconductor chips as a source for broadband wavelength-multiplexed polarization entangled photons.

Generating entangled photons from a monolithic chip is a major milestone towards real-life applications of optical quantum information processing including quantum key distribution and quantum computing. Ultrabroadband entangled photons are of particular interest to various applications such as quantum metrology and multi-party entanglement distribution. In this work, we demonstrate the direct generation of broadband wavelength-multiplexed polarization entangled photons from a semiconductor chip for the first time. Without the use of any off-chip compensation or interferometry, entangled photons with a signal-idler separation as large as 95 nm in the telecom band were observed. The highest concurrence of 0.98±0.01 achieved in this work is also the highest, to the best of our knowledge, comparing to all previously demonstrated semiconductor waveguide sources. This work paves the way for fully integrated, ultrabroadband sources of polarization entangled photons.

Design of a constant-voltage and constant-current controller with dual-loop and adaptive switching frequency control

A 5.0-V 2.0-A flyback power supply controller providing constant-voltage (CV) and constant-current (CC) output regulation without the use of an optical coupler is presented. Dual-close-loop control is proposed here due to its better regulation performance of tolerance over process and temperature compared with open loop control used in common. At the same time, the two modes, CC and CV, could switch to each other automatically and smoothly according to the output voltage level not sacrificing the regulation accuracy at the switching phase, which overcomes the drawback of the digital control scheme depending on a hysteresis comparator to change the mode. On-chip compensation using active capacitor multiplier technique is applied to stabilize the voltage loop, eliminate an additional package pin, and save on the die area. The system consumes as little as 100 mW at no-load condition without degrading the transient response performance by utilizing the adaptive switching frequency control mode. The proposed controller has been implemented in a commercial 0.35-μm 40-V BCD process, and the active chip area is 1.5 × 1.0 mm2. The total error of the output voltage due to line and load variations is less than ±1.7%.

On-Chip Compensated Wide Output Range Boost Converter with Fixed-Frequency Adaptive Off-Time Control for LED Driver Applications

An on-chip compensated wide output range boost converter with fixed-frequency adaptive off-time current-mode control is presented. The small signal characteristic of the boost converter with current-mode control is reviewed, and an adaptive current sensing technique is proposed to reduce the variation of phase margin at different output voltages. On-chip compensation is achieved with a Type II compensator. Adaptive off-time control is adopted for its fast response and no need for slope compensation, while its disadvantage of varying switching frequency is eliminated by the proposed off-time generator. The IC controller was fabricated in a 0.5 μm 2P3M BCD 40 V process. Measurement results confirm that an output range of 5.5 V ~ 36 V with an input voltage of 5 V is achieved. The switching frequency is fixed at 1 MHz with a variation of ±1%. The measured peak efficiency and maximum output power are 92.9% and 8.6 W, respectively. For a load step of 200 mA using a 3.3-μH inductor and a 20-μF output capacitor, overshoot and undershoot of the load transient responses are smaller than 1% of the output voltage.

The on-chip temperature compensation and temperature control research for the silicon micro-gyroscope

In this paper, the on-chip temperature compensation and temperature control research for the silicon micro-gyroscope are presented. The proposed micro-gyroscope architecture which integrates an on-chip temperature sensor and a serpentine micro-heater achieves the on-chip temperature compensation and the on-chip temperature control of the micro-gyroscope. We first analyze the thermodynamic steady-state temperature distribution and transient temperature response of micro-gyroscope structure. Then we simulate the temperature response of the micro-gyroscope structure by Ansys software. The Deep Dry Silicon on Glass process and wet etching process are combined for fabrication of the integrated micro-gyroscope structure. The signal measurement and control circuit based on the FPGA platform are implemented. The temperature coefficients of zero bias and scale factor are compensated with the integrated temperature sensor. Taking advantage of the drive mode resonant frequency as the temperature sensor, a high precision on-chip temperature control of micro-gyroscope is realized simultaneously. The on-chip temperature compensation and temperature control experiment of micro-gyroscope prototype is tested. Experimental results indicate that the temperature coefficients of the scale factor and zero bias decrease by 3.95 times and 3.49 times separately by on-chip temperature compensation, which optimizes significantly the temperature characteristics of the micro-gyroscope prototype. The control accuracy of drive-mode frequency reaches to 3.57 × 10?4 Hz (that is 0.123 ppm and the calculated temperature accuracy of 0.0067 °C) from 0 to 40 °C by the on-chip temperature control, which demonstrates an achievement of the precision on-chip temperature control for the micro-gyroscope.

Area‐ and power‐efficient DC–DC converter with on‐chip compensation

A dual-path capacitor multiplier (DPCM) technique is proposed for on-chip frequency compensation. The DPCM uses two currents to charge and discharge a compensation capacitor concurrently. Consequently, the equivalent capacitance is amplified dramatically with slight increase in silicon area and power. Thanks to the DPCM, the transient response of the DC-DC converter has improved significantly because of the small compensation capacitor. Experimental results demonstrate converter stability and transient response. The transient recovery time of a 450 mA step load change is <;30 μs. With the proposed technique, the compensation capacitor is shrunk significantly and adding the compensation resistor would have helped in improving transient response.