On-chip Compensation Research Articles

An offset compensated and high-gain CMOS current-feedback op-amp

This work describes a new CMOS current-feedback operational amplifier (CFOA) with an on-chip continuous-time current-mode input offset voltage compensation circuit. The proposed compensation method is based on a combination of two techniques: the error integration and the current feedback. In addition, this method is irrespective of process and temperature parameters because of its fully symmetrical architecture. HSPICE simulations of the designed CMOS CFOA layout show that the input offset voltage could be reduced to lass than 1 mV, and a gain of around 112 dB and a power consumption of less than 3 mW are achievable.

Silicon pressure sensor with integrated CMOS signal-conditioning circuit and compensation of temperature coefficient

A silicon pressure sensor designed for automotive applications with on-chip signal conditioning is presented. The micromechanical processing steps are added to a standard 3 μm CMOS process. The membrane is etched in (100)-oriented Si by anisotropic etching with an electrochemical etch stop. Thickness control with tolerances of less than 0.5 μm is readily achieved. A complete CMOS evaluation circuit is integrated on the same device. The signal of the piezoresistive Wheatstone bridge is processed by an instrumentation amplifier with temperature-dependent amplification for on-chip compensation of the sensitivity variation with temperature. Moreover, the sensitivity variation itself, the offset and the offset variation with temperature are compensated. On-chip trimming is provided for the adjustment of these terms in the full automotive temperature range from −40 °C to + 125 °C.

An interchangeable silicon pressure sensor with on-chip compensation circuitry

A new concept for the calibration and temperature compensation of a piezoresistive silicon pressure sensor is proposed, in which the piezoresistive Wheatstone bridge is combined on chip with a trimmable polysilicon resistor network. The design, fabrication and measured characteristic of a sensor based on this concept are presented.

Novel circuit technology for ECL-compatible GaAs static RAMs with small access time scattering

A novel circuit technology has been developed to realize GaAs SRAMs suitable for use in real-system environments. It has achieved Si ECL compatibility through the use of an ECL 100 K-compatible input buffer circuit with on-chip reference compensation. Wide V/SUB th/ tolerance and an improved noise margin have been obtained through the use of a novel normally-on-type circuit called the FET logic with Schottky diode and coupling capacitor (FLSC). Two experimental ECL-compatible GaAs SRAMs (256-word/spl times/4-b and 1024-word/spl times/4-b) were designed and successfully fabricated using this technology. In the 4 K SRAM, an access time of 2.2-3.0 ns with a power dissipation of 890 mW was achieved and the normal read/write operation at 4-ns cycle time was also confirmed.