Output capacitor-free low-dropout regulator with fast transient response and ultra small compensation capacitor

Abstract

A output capacitor-free low-dropout regulator (LDO) with fast transient response and ultra-small compensation capacitor is proposed. The slew-rate enhancement (SRE) circuit based on dynamic biasing technique is designed to improve load transient response for 100mA load step. The SRE circuit structure does not use any passive element to save silicon area and cost. The total active area of the proposed LDO is 0.043mm2 with 0.4pF on-chip compensation capacitor and the stability analysis is also included. The proposed LDO is implemented in 0.35µm process and experimental results show that it regulates the output voltage at 1.8V and 1V with dropout voltage of 200mV, 100mA maximum output-load current. The measured quiescent current is 15 μA only. For a 2V input voltage, the proposed LDO is able to regulate output voltage of 1.8V within 2μs with less than 148mV overshoot and undershoot. For a 1.2V input voltage, the LDO is able to regulate output voltage of 1V within 3μs with less than 152mV overshoot and undershoot.