Abstract
This paper presents a low drop-out (LDO) regulator using an active feedback frequency compensation (AFFC) structure for compensation. By eliminating the right-half-plane zero and bringing a left one, the phase margin and the stability can be improved. And the compensation loop reuses the current in the first stage to minimize the quiescent current. A slew-rate enhancement circuit is presented to speed up transient response. The LDO regulator provides full range stability from 0 to 100mA load current. The LDO is simulated in a 0.18um CMOS process, supplying 1.6V with a dropout voltage of 181mV. The quiescent current is 29uA for 100pF load capacitor.
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