A Capacitor-less Low Drop-out (LDO) Regulator with Improved Transient Response for System-on-Chip Applications

Abstract

This paper presents a capacitor-less low drop-out (LDO) regulator with a slew-rate enhancement circuit. The proposed slew-rate enhancement circuit senses the transient voltage at the output of the LDO to increase the bias current of the error amplifier for a short duration. Hence, the transient response of the regulator is significantly improved due to the enhancement of the slew-rate at the gate of the pass transistor. The proposed LDO regulator has been designed and simulated in UMC 0.18 μm standard CMOS process. Simulation results show that, the LDO regulator consumes a quiescent current of 40 μA only. It regulates the output voltage at 1.2 V from a 1.4 V - 1.8 V supply, with a minimum drop-out voltage of 200 mV at the maximum output current of 100 mA. With the proposed LDO regulator, the amount of overshoot/undershoot in the output voltage under extreme load transients and the settling time of the regulator are 75 mV/ 71 mV and 1.172 μs/ 1.055 μs respectively for a load slew-rate of 99 mA / 1 μs. The proposed LDO regulator has recorded an improvement of 60.9% in terms of the settling time in the post-layout simulation when compared to previously published work.