OFF Ratio Research Articles

Investigation of Reliability Issues in a hybrid Extended Dual Source Double Gate Tunnel FET

This paper presents the design and analysis of an enhanced tunnel field-effect transistor (TFET) structure. The proposed structure comprises a dual source and a double gate, aiming to enhance the DC characteristics of the TFET. The dual source concept is used in the structure with two homogeneous gates, which play a major role in boosting the tunneling parameters. It also examines the affectability of source dimensions and drain doping on the performance of the proposed device. Furthermore, we have compared our proposed structure with the single source device. The proposed device after optimization exhibits an extraordinary I ON/I OFF ratio of 2.33 × 1013, with an I OFF of 6.25 × 10−19A/µm, and decent I on of 1.46 × 10−5A/µm along with a subthreshold swing (SS) of 43 mV/dec. The device characteristics have been analyzed in the presence of interface traps. The electrical parameters have been quantified against various types and concentrations of traps. The performance of the proposed device has been compared with the existing TFET structures.

High-Performance WS2 MOSFETs with Bilayer WS2 Contacts.

WS2 is a promising transition-metal dichalcogenide (TMDC) for use as a channel material in extreme-scaled metal-oxide-semiconductor field-effect transistors (MOSFETs) due to its monolayer thickness, high carrier mobility, and its potential for symmetric n-type and p-type MOSFET performance. However, the formation of stable, low-barrier-height contacts to monolayer TMDCs continues to be a challenge. This study introduces an innovative approach to realize high-performance WS2 MOSFETs by utilizing bilayer WS2 (2L-WS2) in the contact region grown through a two-step chemical vapor deposition process. The 2L-WS2 devices demonstrate a high I ON/I OFF ratio of 108 and a saturated drain current, I D(SAT), of 280 μA/μm (386 μA/μm) at room temperature (78 K), even while still using conventional metal (Pd or Ni) contacts. Devices featuring a 1L-WS2 channel and 2L-WS2 in the contact regions were also fabricated, and they exhibited performance comparable to that of 2L-WS2 devices. The devices also exhibit good stability with nearly identical performance after storage over a 13 month period. The study highlights the benefits of a hybrid channel thickness approach for TMDC transistors.

Performance and reliability assessment of source work function engineered charge plasma based Ti/HfO2/Al2O3/Ge, double gate TFET

The Tunnel Field Effect Transistor (TFET) often suffers from low ON current (I ON), charge traps, and thermal variability, which limits its performance and reliability. To address these issues, the source work function engineered Ge Charge Plasma Double Gate Tunnel Field Effect Transistor (CP-DGTFET) device structure with HfO2/Al2O3 bilayer gate dielectric is designed and investigated using numerical TCAD simulations. The proposed Ti/HfO2/Al2O3/Ge CP-DGTFET device structure showed excellent DC characteristics with exceptional I ON, I ON/I OFF ratio, and minimal sub-threshold swing (S) of ∼3.04 × 10−4 A μm−1, ∼1.2 × 1010, and ∼3.4 mV/dec, respectively. Furthermore, the device’s analog characteristics displayed good transconductance, cut-off frequency, and gain bandwidth product of ∼0.75 mS/μm, ∼0.97 THz, and ∼102 GHz, respectively. Moreover, the charge trap exploration divulges that positive ITCs can enhance device performance, whereas negative ITCs can adversely impact the electrical characteristics of CP-DGTFET. Additionally, the temperature-dependent analysis showed that the OFF-state leakage current increases from ∼1.7 × 10−15 A μm−1 to 2.4 × 10−10 A μm−1 with temperature fluctuations from 275 K to 375 K. Overall, the work function-engineered CP-based Ti/HfO2/Al2O3/Ge DGTFET device structure shows great potential for improving the performance and reliability of Ge TFET technology.

Analysis of Negative Capacitance Source Pocket Double-Gate TFET with Steep Subthreshold and High ON–OFF Ratio

Analysis of Negative Capacitance Source Pocket Double-Gate TFET with Steep Subthreshold and High ON–OFF Ratio

Stacked structure dependence on resistive switching characteristics in sumanene molecular memory

Nonvolatile memories using molecule (molecule memories) are attracting attention. This is because these materials are suitable for miniaturization and higher capacity of memories in terms of their properties and dimensions. We have already demonstrated that the metal–insulator–metal (MIM) devices with sumanene-inserted bilayer graphene show huge resistive switching characteristics. However, the reason why resistive switching occurs in the graphene/sumanene/graphene structure has yet to be clarified. In this work, to investigate the mechanisms of the resistive switching phenomenon in sumanene-inserted bilayer graphene, plural kinds of stacked MIM structures are fabricated and evaluated. As a result, the measurement results clearly show that the graphene/sumanene/graphene structure is indispensable in the resistive switching phenomenon. Furthermore, based on the temperature dependence of the resistive switching, it is confirmed that a significant I ON/I OFF ratio can be obtained at higher operation temperatures.

Design and performance analysis of tri-layered strained Si/Si1–x Ge x /Si heterostructure DG feedback FET

This work presents the design and performance analysis of a tri-layered strained Si/Si1−x Ge x /Si heterostructure double gate feedback field-effect transistor (DG FBFET). The proposed DG FBFET is designed by introducing biaxial strain in the device by sandwiching a Si1−x Ge x layer between two thin Si layers to provide high ON current as well as ultra-steep switching characteristics. The device offers a significantly high ON current (3.4 x 10−3 A/μm), high I ON /I OFF ratio (∼1010), a large memory window of 1.06 V, and an extremely low subthreshold swing (∼0.3 μ V/decade), which can be very useful for memory and neuromorphic applications. Furthermore, the ON/OFF switching of the device has been accomplished at a lower threshold voltage (0.287 V), allowing it to be utilized in low-power electronics. Synopsys TCAD tool has been used to create the device structure and analyze the electrical performances of the device.

Toward Sustainability in All‐Printed Accumulation Mode Organic Electrochemical Transistors

AbstractThis study reports on the first all‐printed vertically stacked organic electrochemical transistors (OECTs) operating in accumulation mode; the devices, relying on poly([4,4′‐bis(2‐(2‐(2‐methoxyethoxy)ethoxy)ethoxy)‐2,2′‐bithiophen‐5,5′‐diyl]‐alt‐[thieno[3,2‐b]thiophene‐2,5‐diyl]) (pgBTTT) as the active channel material, are fabricated via a combination of screen and inkjet printing technologies. The resulting OECTs (W/L ≈5) demonstrate good switching performance; gm, norm ≈13 mS cm−1, µC* ≈21 F cm−1 V−1 s−1, ON–OFF ratio > 104 and good cycling stability upon continuous operation for 2 h. The inkjet printing process of pgBTTT is established by first solubilizing the polymer in dihydrolevoglucosenone (Cyrene), a non‐toxic, cellulose‐derived, and biodegradable solvent. The resulting ink formulations exhibit good jettability, thereby providing reproducible and stable p‐type accumulation mode all‐printed OECTs with high performance. Besides the environmental and safety benefits of this solvent, this study also demonstrates the assessment of how the solvent affects the performance of spin‐coated OECTs, which justifies the choice of Cyrene as an alternative to commonly used harmful solvents such as chloroform, also from a device perspective. Hence, this approach shows a new possibility of obtaining more sustainable printed electronic devices, which will eventually result in all‐printed OECT‐based logic circuits operating in complementary mode.

Photoconductivity in self-assembled CuO thin films

Self-assembly is the most promising low-cost and high-throughput methodology for nanofabrication. This paper reports the optimization of a self-assembly process at room temperature for the growth of copper oxide (CuO) based nanostructures over a copper substrate using aqueous potassium hydroxide (KOH) solution as the oxidizing agent. The monoclinic phase of CuO nanostructures grown over the copper substrate was confirmed from the X-ray diffraction (XRD) and micro-Raman analysis. The overall chemical composition of nanostructures was confirmed to be that of CuO from its oxidation state using X-ray photoelectron spectroscopy (XPS). Photodetectors were engineered with the structure Cu/CuO/Ag. The photodetectors exhibited a response to both ultraviolet and visible light illumination. The optimized Cu/CuO/Ag structure exhibits a responsivity of ~ 1.65 µA/W, with an ON:OFF ratio of ~ 69 under a bias voltage of 0.01 V. The temporal dependence of photo-response for the optimized photodetector displayed the persistent nature of photoconduction indicating a delay in charge carrier recombination which could potentially be exploited for photovoltaic applications.

Modeling of 1S-1R crossbar array with Ti-doped VO2-based selector device

This article proposes a Ti-doped Vanadium dioxide (VO2) selector device for reducing the leakage current. Here, TiO2 is formed by the Ti atoms in the VO2 film for acting like a good insulator. Hence, it reduces the integration density when the leakage current in a Cross Bar Array (CBA) is increased. In this article, the modeled Pt/Ti-doped VO2/Pt selector device is integrated with the resistive random-access memory model to demonstrate its effectiveness on sneak path current reduction. The I ON / I OFF ratio of the suggested Ti-doped VO2 selector is higher than 2 × 1 0 4 . The simulated results outputs in terms of nonlinearity (∼ 28 × 1 0 4 ), current density (∼ 10 7 A cm − 2 ), and leakage current(∼0.31nA).

Design and performance analysis of Si-SiGe heterostructure based double gate feedback FET

The design and performance analysis of a Si-SiGe heterostructure-based double gate feedback field-effect transistor (HDG FBFET) are presented in this paper. The proposed HDG FBFET is capable of providing high on current (3 × 10−4 A/μm) with a large I ON /I OFF ratio (3 × 1011) and is scalable up to 20 nm channel length. Its exceptionally steep switching characteristics (SS < 1 mV/decade) and ability to switch ON/OFF at lower gate voltage due to the use of smaller band-gap material (Si1−x Ge x ) in channel-2 and drain regions make it suitable for use in low power applications. A significant hysteresis window of 4.99 V is also achieved by the device, which can be extremely helpful for memory applications. Moreover, a comprehensive investigation of the nature of hysteresis in relation to the different device parameters has also been carried out. The designing of the device structure and all of the electrical performance characterization have been done using the Sentaurus TCAD tool.

Oppositely-Doped Core-Shell Junctionless Nanowire FET: Design and Investigation

Junctionless Nanowire Field Effect Transistor (JL-NWFET) has garnered significant attention in recent years owing to its simplified fabrication process, achieved through uniform doping across the device. However, JL-NWFET suffers from certain drawbacks, including low drive current, insufficient volume depletion, and lateral band-to-band tunneling. To address these issues, this paper proposes Improved JL-NWFET with an oppositely doped core–shell structure along with a Dual Material gate (DMG) and high-k spacer. Furthermore, Improved JL-NWFET is optimized for parameters such as core thickness, gate oxide material, spacer material, and spacer length. The performance of Improved JL-NWFET is also evaluated in comparison with other structural variants of JL-NWFET. Notably, Improved JL-NWFET showcases an enhancement of 23.1% and 20% in ON-state current (I ON ) and transconductance (g m ), respectively when compared to the conventional JL-NWFET. Furthermore, the Subthreshold Slope (SS) experiences an 88% improvement in the Improved JL-NWFET as opposed to the JL-NWFET. Additionally, the OFF-state leakage current (I OFF ) undergoes a fivefold reduction, leading to a sixfold increase in the I ON /I OFF ratio compared to the JL-NWFET. Among all the variants of JL-NWFET devices analyzed in this paper, Improved JL-NWFET stands out with its exceptional performance characteristics.

Flexible SnO2–MoS2 based memristive device exhibiting stable and enhanced memory phenomenon

Flexible non-volatile memory devices have been gaining interest in expanding the digital data storage world. Due to the burgeoning advancement in the healthcare industry, the Internet of Things, and wearable electronics, the demand for ultra-thin, low-power, and flexible memory is increasing. Further, the advancement of synthesis procedures for two-dimensional nanomaterials having better optical, electrical, and mechanical strength with flexibility has fuelled the flexible memory device area, as commonly used flash memory is approaching its physical limit. In this context, the present work reports the flexible resistive switching memory device based on pure molybdenum disulfide (MoS2) and tin oxide (SnO2) based nanocomposite powder synthesized using the simple hydrothermal process. The nanocomposite formation was characterized using x-ray diffraction and Raman spectroscopic techniques. The memory device was fabricated by spin-coating the pure MoS2, pure SnO2, and MoS2–SnO2 nanocomposite film over the ITO-PET flexible substrate. The device was completed by thermally evaporating the thin Al layer through a shadow mask. It was found that MoS2–SnO2 based memory devices exhibited improved switching performance having a higher I ON/I OFF ratio, and lower switching voltage in comparison to pure MoS2 and pure SnO2-based devices (I ON/I OFF ratio ∼100, V = 0.5 V). Furthermore, to check the stability and cyclic performance of the fabricated device, the retention and endurance test was also performed, and the MoS2–SnO2 device retained the HRS and LRS states up to 2 × 103s and showed stable performance up to 100 switching cycles without much degradation, respectively. It should be mentioned that the presently proposed ReRAM device based on SnO2 and MoS2 with flexible and low-power features had excellent potential for use in the wearable device industry.

Quaternary, layered, 2D chalcogenide, Mo1−x W x SSe: thickness dependent transport properties

Highly oriented, single crystalline, quaternary alloy chalcogenide crystal, Mo x W1−x S2y Se2(1−y), is synthesized using a high temperature chemical vapor transport technique and its transport properties studied over a wide temperature range. Field effect transistors (FET) with bottom gated configuration are fabricated using Mo0.5W0.5SSe flakes of different thicknesses, from a single layer to bulk. The FET characteristics are thickness tunable, with thin flakes (1–4 layers) exhibiting n-type transport behaviour while ambipolar transfer characteristics are observed for thicker flakes (>90 layers). Ambipolar behavior with the dominance of n-type over p-type transport is noted for devices fabricated with layers between 9 and 90. The devices with flake thickness ∼9 layers exhibit a maximum electron mobility 63 ± 4 cm2 V−1s−1 and an I ON/I OFF ratio >108. A maximum hole mobility 10.3 ± 0.4 cm2 V−1s−1 is observed for the devices with flake thickness ∼94 layers with I ON/I OFF ratio >102–103 observed for the hole conduction. A maximum I ON/I OFF for hole conduction, 104 is obtained for the devices fabricated with flakes of thickness ∼7–19 layers. The electron Schottky barrier height values are determined to be ∼23.3 meV and ∼74 meV for 2 layer and 94 layers flakes respectively, as measured using low temperature measurements. This indicates that an increase in hole current with thickness is likely to be due to lowering of the band gap as a function of thickness. Furthermore, the contact resistance (R ct) is evaluated using transmission line model (TLM) and is found to be 14 kohm.μm. These results suggest that quaternary alloys of Mo0.5W0.5SSe are potential candidates for various electronic/optoelectronic devices where properties and performance can be tuned within a single composition.

Study of enhancement-mode GaN pFET with H plasma treated gate recess

This letter showcases the successful fabrication of an enhancement-mode (E-mode) buried p-channel GaN field-effect-transistor on a standard p-GaN/AlGaN/GaN-on-Si power HEMT substrate. The transistor exhibits a threshold voltage (V TH) of −3.8 V, a maximum ON-state current (I ON) of 1.12 mA/mm, and an impressive I ON/I OFF ratio of 107. To achieve these remarkable results, an H plasma treatment was strategically applied to the gated p-GaN region, where a relatively thick GaN layer (i.e., 70 nm) was kept intact without aggressive gate recess. Through this treatment, the top portion of the GaN layer was converted to be hole-free, leaving only the bottom portion p-type and spatially separated from the etched GaN surface and gate-oxide/GaN interface. This approach allows for E-mode operation while retaining high-quality p-channel characteristics.

Bilateral sidewall engineering Si1–x Ge x iTFET for low power display application * *This work was supported in part by the Ministry of Science and Technology of Taiwan, R.O.C., under Contact MOST109–2221-E-110–018-MY3.

In this work, we demonstrate the performance enhancement of bottom-gated inductive line-tunneling TFET (iTFET) through the integration of bilateral sidewall engineering with SiGe mole fraction variation, considering the feasibility of the fabrication process. We also employ a metal-semiconductor interface for carrier induction to improve the I ON, resulting in a lower subthreshold swing average (S.S avg). Using Sentaurus TCAD simulations, we show that the dominant current mechanism is line tunneling, and the hump effect is mitigated by using SiGe with different mole fractions on the sidewalls. Compared to conventional tunnel field-effect transistors, which require at least three doping processes and annealing, the proposed device requires only one doping process and utilizes the metal-semiconductor interface for carrier induction, significantly reducing the fabrication cost and thermal budget. These measurement based simulations show that the S.S avg is improved to 21.5 mV dec−1 with an I ON/I OFF ratio of 106 at V D = 0.2 V. This is the first time that a TFT with a subthreshold swing of less than 60 mV dec−1 has been proposed, so it will save much more power in the future and displays with high energy efficiency can be realized and widely used in IoT applications.

High-performance enhancement-mode GaN-based p-FETs fabricated with O3-Al2O3/HfO2-stacked gate dielectric

In this letter, an enhancement-mode (E-mode) GaN p-channel field-effect transistor (p-FET) with a high current density of −4.9 mA/mm based on a O3-Al2O3/HfO2 (5/15 nm) stacked gate dielectric was demonstrated on a p++-GaN/p-GaN/AlN/AlGaN/AlN/GaN/Si heterostructure. Attributed to the p++-GaN capping layer, a good linear ohmic I−V characteristic featuring a low-contact resistivity (ρ c) of 1.34 × 10−4 Ω·cm2 was obtained. High gate leakage associated with the HfO2 high-k gate dielectric was effectively blocked by the 5-nm O3-Al2O3 insertion layer grown by atomic layer deposition, contributing to a high I ON/I OFF ratio of 6 × 106 and a remarkably reduced subthreshold swing (SS) in the fabricated p-FETs. The proposed structure is compelling for energy-efficient GaN complementary logic (CL) circuits.

Bismuth sulfide based resistive switching device as the key to advanced logic gate fabrication

A memristor is a two-terminal electrical component with the scope of future computing applications and analog electronics. In this report, bismuth sulfide decorated one-dimensional carbon nitride nanotube was synthesized and characterized with various analytical techniques. The electrical property of the synthesized material was measured using a two-terminal metal–insulator–metal type of device that exhibited the resistive switching characteristics with the ON to OFF ratio of 2 × 103. The electron transport mechanism of the device was followed by Schottky emission and Poole–Frenkel emission for a low conductance state and Ohmic conduction behavior at the high conductance state. A decrease in the trap depth was identified in the simulation study with increasing applied potential and that supported the proposed mechanism. Read endurance and retention behavior of the device are stable in nature, supported by the statistical analysis. Furthermore, a hybrid logic gate was designed using two identical memristors, one CMOS inverter, one resistor, one voltage divider, and a buffer gate. The designed logic gate exhibited stable nand and nor gate operation based on the control signal.

A low-power SRAM design with enhanced stability and ION/IOFF ratio in FinFET technology for wearable device applications

ABSTRACT Wearable device applications such as smartwatches, fitness trackers, and health monitors rely on batteries for power and require static random-access memory (SRAM) with low power consumption and high stability to ensure accurate sensor readings during prolonged operation. In this regard, this paper proposes a novel low-power single-ended 10-transistor (SE10T) SRAM cell with high stabilities. It utilises a stacked pull-down structure for hold/read stability improvement and leakage power reduction, a feedback-cutting mechanism for writability enhancement, and single-ended read/write structures for dynamic power reduction. Also, using a single-transistor reading path with eliminated read bitline leakage enhances ON-to-OFF currents (I ON /I OFF ) ratio. The proposed design is compared with the conventional 6T, Schmitt-trigger 10T (ST10T), differential writing 10T (DW10T), data-independent read port 10T (DIRP10T), transmission gate read-decoupled 9T (TGRD9T), and feedback-cutting 11T (FC11T) SRAM cells based on 7-nm Fin-shaped Field-Effect Transistor (FinFET) technology at V DD = 0.4 V. The proposed design shows at least 1.04×/1.01×/1.12×/1.25×/1.15× improvement in read stability/writability/read delay/leakage power/dynamic power. Moreover, it shows at least 1.22× improvement in I ON /I OFF ratio and offers the lowest minimum operating voltage (0.292 V). However, it offers a 1.02× lower hold stability than that of ST10T, a 1.18×/1.14×/1.13× higher write delay compared to 6T/ST10T/DW10T, and a 1.56×/1.07×/1.05× higher layout area occupation in comparison with 6T/TGRD9T/DIRP10T. Therefore, the proposed SRAM cell can be an optimum candidate for usage in smartwatches.

Laser‐Induced Graphene Electrodes for Organic Electrochemical Transistors (OECTs)

AbstractOrganic electrochemical transistors (OECTs) have drawn significant interest because of their low cost, biocompatibility, and ease of fabrication, allowing them to be utilized in various applications including flexible displays, electrochemical sensing, and biosensing. Key components of OECTs are the gate, source, and drain electrodes. Herein, OECTs with laser‐induced graphene (LIG) electrodes are demonstrated. The electrode patterns for the source, drain, and gate are created by converting the polymer substrate polyimide (PI) into LIG using a scanned laser. The process is simple and inexpensive without complicated chemical synthesis routines or expensive materials such as gold. Patterns can be customized quickly and digitally. The low‐cost and porous LIG electrodes with low contact resistance and good electrical stability play an essential role in device performance. The minimum sheet resistance achieved with this laser method for the square patterned electrodes is 7.86 Ω sq−1. The LIG‐based OECTs demonstrate good electrical modulation with ON–OFF ratio of 72.80 and high ON current on the order of mA. The LIG‐based OECTs exhibit comparable or better performance in comparison with other reports of OECTs on plastic substrates using more complex fabrication methods in terms of OFF current, ON current, transconductance (gm), and contact resistance.

MoS2-functionalized conductive carbon heterostructure embedded with ferroelectric polymers for bipolar memristive applications

Heterostructures of two-dimensional layered materials, integrating two or more building blocks with complementing counterparts, can regulate the confinement and transportation of charge carriers via vacancy-induced defect and interfacial states. Herein, reduced graphene oxide-molybdenum disulfide (rGO-MoS2) nanohybrid were fabricated and reinforced with various polymers [poly methyl methacrylate (PMMA), poly (vinylidene fluoride) (PVDF), and PMMA-PVDF (20:80) blend] to study the resistive memory properties in a metal–insulator-metal configuration. The scanning electron microscopy analysis presents a hierarchical 3D flower-like MoS2 intercalated with rGO nanosheets. Transmission electron microscopy image exhibits MoS2 nanoflakes well interspersed and grafted on layered rGO sheets, forming sandwich heterostructures. Raman analysis shows a higher I D/I G ratio for rGO-MoS2 than rGO, demonstrating numerous defect states in rGO. The x-ray diffraction analysis of the polymer blend containing rGO-MoS2 exhibits β-crystal phases with a polarity-dependent internal electric field (E-field). The J-V characteristics of pure MoS2-polymer films display a write-once-read-many behavior with a current I ON/I OFF ratio of ∼102–103, in contrast to pristine polymer films exhibiting repeatable electrical hysteresis. Instead, the rGO-MoS2-based devices display bipolar characteristics (I ON/I OFF ratio of ∼103–104) due to charge transfer interaction with the conductive carbon substrates. The ferroelectric polarization-induced E-field coupled with the external bias is responsible for the improved memristive performances. A plausible conduction mechanism is proposed to discuss the carrier transport through the devices.