Noise Margin Research Articles

Design of power efficient and reliable hybrid inverter approach based 11 T SRAM design using GNRFET technology

Designing a power efficient and high-speed static random-access memory (SRAM) cell with improved noise stability using traditional complementary metal oxide semiconductor (CMOS) devices is an arduous task. Owing to balanced electrical properties of graphene nanoribbon field-effect transistor (GNRFET), its capability to realize high performance SRAM cells need a keen exploration. This article proposes an 11-transistor GNRFET SRAM cell which deploys hybrid inverter scheme. The hybrid inverter scheme encompasses two distinct inverters, based on stacked transistors and Schmitt trigger (ST) techniques. The simulations conducted using 16 nm GNRFET model in HSPICE simulator show that proposed SRAM cell has write power, hold power, read power, write static noise margin, hold static noise margin, read static noise margin, write delay and read delay of 0.445 nW, 0.978 µW, 1.8 nW, 225 mV, 222.8 mV, 225.1 mV, 24 pS and 49.6 pS, respectively. The results obtained for proposed SRAM cell have been found to be encouraging in contrast to previously reported SRAM cells implemented using 16 nm GNRFET model. Besides this, the effect of variation in various parameters of GNRFET on performance of proposed SRAM cell has been investigated in this article. The outstanding performance results of SRAM makes its suitable for developing high performance memories devices for biomedical digital gadgets, internet of things (IoT), artificial intelligence (AI) and smart agricultural applications.

Improved post-radiation behavior of FinFET based CMOS with workfunction modulated gate

The total ionizing dose (TID) effect of modulated gate workfunction (MGW) FinFET based CMOS inverter is designed and analyzed. The post radiation analysis of the voltage transfer characteristics, noise margin and propagation delay are demonstrated. The incorporation workfunction modulation engineering enhances the OFF-state performance, and maintains positive threshold voltage for both the pre and post radiation condition. 2-decade improvement is noticed for the both n-FinFET and p-FinFET. In addition, the proposed technique offers minimum propagation delay time and acceptable noise margin range even after 2000 krad of radiation dose. The analysis and comparison of the results is done by the 3-D TCAD simulator.

Interaction of Negative Bias Instability and Self-Heating Effect on Threshold Voltage and SRAM (Static Random-Access Memory) Stability of Nanosheet Field-Effect Transistors.

In this paper, we investigate the effects of negative bias instability (NBTI) and self-heating effect (SHE) on threshold voltage in NSFETs. To explore accurately the interaction between SHE and NBTI, we established an NBTI simulation framework based on trap microdynamics and considered the influence of the self-heating effect. The results show that NBTI weakens the SHE effect, while SHE exacerbates the NBTI effect. Since the width of the nanosheet in NSFET has a significant control effect on the electric field distribution, we also studied the effect of the width of the nanosheet on the NBTI and self-heating effect. The results show that increasing the width of the nanosheet will reduce the NBTI effect but will enhance the SHE effect. In addition, we extended our research to the SRAM cell circuit, and the results show that the NBTI effect will reduce the static noise margin (SNM) of the SRAM cell, and the NBTI effect affected by self-heating will make the SNM decrease more significantly. In addition, our research results also indicate that increasing the nanosheet width can help slow down the NBTI effect and the negative impact of NBTI on SRAM performance affected by the self-heating effect.

Tunable optoelectronic response in van der Waals heterojunction transistors for artificial visual recognition

Optoelectronic synaptic transistors are advantageous in in-memory light sensing for artificial neural networks. Herein, optoelectronic synaptic junction field-effect transistors (JFETs) based on a Ga2O3/MoS2 heterojunction are fabricated. The devices exhibit robust electrical performances, including a high on/off ratio of 108, a low subthreshold swing of 69 mV dec−1, and a high output current of 3.4 μA μm−1. An inverter and a NAND gate are constructed based on the dual-gated configuration, with the inverter showing a high voltage gain of 28 and the near-ideal noise margin of 90.4%. Additionally, the devices demonstrate outstanding optoelectronic performances benefiting from the strong light–matter interactions of MoS2. Typical synaptic plasticities, including short-term plasticity, long-term plasticity, and spiking-rate-dependent plasticity, are simulated by applying the light pulses. Furthermore, metaplastic excitatory postsynaptic current, metaplastic facilitation of long-term potentiation and transition from potentiation to depression are also readily demonstrated. The artificial neural network, in which neurons are interconnected through our proposed optoelectronic synaptic transistors, achieves a high accuracy of 89.8% in recognizing handwritten digits. This work provides insight into the design of an optoelectronic synapse based on JFETs.

Radiation tolerant capacitor-SRAM without area overhead

In memory semiconductors such as a static random access memory (SRAM), a common problem is soft errors under radiation environment. These soft errors cause bit flips, which are referred to as single event upsets (SEUs). Some radiation-hardened SRAM cells such as a Quatro SRAM, we-Quatro SRAM, and DICE SRAM cells have been reported for years. However, these designs have the disadvantage of taking up more area than a conventional 6T SRAM cell. Thus, we propose a radiation-hardened SRAM cell design that we named capacitor-static random access memory (C-SRAM) without area overhead. The C-SRAM is formed by simply adding a capacitor to the conventional 6T SRAM. It was designed to mitigate the radiation effect using the conservation law of electrical charge. Moreover, it has the same cell size as the conventional 6T SRAM cell. Its static noise margins (SNMs), which are indicators of operational stability, are equal to the conventional 6T SRAM values of 530 mV, 220 mV, and 860 mV in hold, read, and write modes, respectively. The results of the SEU simulation test showed that it had 4.761 times better flipping tolerance than the conventional 6T SRAM with a charge value of 247.494 fC. In addition, irradiation experiments also confirmed that the C-SRAM cell was more tolerant than the 6T SRAM cell. The conventional 6T SRAM and C-SRAM were fabricated using a standard 0.18 μm CMOS process.

Cd0.2Zn0.8O nanowire thin film transistor for low kickback high-speed AMLCD circuit applications

This paper reports the Cd0.2Zn0.8O channel cylindrical gate-all-around nanowire thin-film transistor (CY-GAA-NWTFT) for high-speed active-matrix liquid crystal display (AMLCD) pixel circuit with minimal kickback voltage. The AC/DC, analog, and energy efficiency of this device are investigated against the variation in lateral (channel length) as well as vertical dimension (oxide thickness) using technology computer aided design (TCAD) device simulation environment. Further, the behavior of CY-GAA-TFT is crosschecked by implementing it on resistive load digital inverter circuit followed by transient analysis to calculate delay of the inverter circuit. Moreover, static analysis has been also performed to evaluate its voltage transfer curve (VTC) to derive its noise margin and voltage gain. The execution of the proposed CY-GAA-NWT device on AMLCD pixel circuit indicates tremendous improvement in performance in terms of high-speed applications and low kickback voltage.

High-mobility wide bandgap amorphous gallium oxide thin-film transistors for NMOS inverters

Wide bandgap gallium oxide thin-film transistor (TFT) is promising for next-generation sustainable energy-efficient power electronics. In particular, amorphous oxide channel exhibits inherent advantages on mass productions based on a low-temperature processability compatible with cost-effective large-sized glass. Here, we developed hydrogen defect termination to produce amorphous-GaOx (a-GaOx) channel for n-channel oxide-TFT and demonstrated high-mobility a-GaOx-TFT exhibiting a high saturation mobility (μsat) of ∼31 cm2 V−1 s−1, threshold voltage (Vth) of ∼3.3 V, a current on/off ratio of ∼108, and subthreshold swing value (s-value) of ∼1.17 V·dec−1. The study found that oxygen conditions during the channel fabrication process, i.e., oxygen partial pressure during the film deposition and post-thermal annealing atmospheres, were critical for the TFT performances of gallium oxide-TFTs, and subgap defects originated from low-valence Ga+ state and excess oxygen rather than oxygen vacancy had a large responsibility for the device performances. The finding explains why the development of gallium oxide-TFTs is largely behind the other oxide-TFTs. We also fabricated depletion and enhancement-mode a-GaOx-TFTs and developed a full-swing zero-VGS-load inverter with high voltage gain ∼200 and sufficient noise margins. The present study demonstrates a high potential of gallium oxide channel for low-temperature processed n-channel oxide-TFT for next-generation electronic applications.

Impact of TID Irradiation on Static Noise Margin of 22 nm UTBB FD-SOI 6-T SRAM Cells

Impact of TID Irradiation on Static Noise Margin of 22 nm UTBB FD-SOI 6-T SRAM Cells

A novel step architecture based negative capacitance (SNC) FET: Design and circuit level analysis

This study investigates the effects of temperature on RF/Analog and linearity parameters using a 3 nm technology node Step-Negative capacitance FinFET (SNC-FinFET) for the first time. The SNC-FinFET exhibits superior performance compared to the conventional step architecture, with an enhancement of 7.2% in ION (ON-current), 73.58% in IOFF (OFF-current), excellent SS (Sub-threshold Swing) of 57.51 mV/decade, and a barrier rising of 52.38%. This is due to prior DC analysis that led to the extraction of the electrical parameters such as ION, IOFF, SS and threshold voltage (VT). After that, dimensional analysis is being done in terms of gate length (LG), fin widths (Wfin1 and Wfin2), and fin heights (Hfin1 and Hfin2). The optimized dimensions for this study are LG = 18 nm, Wfin1 = 5 nm, Wfin2 = 3 nm, Hfin1 = 50 nm, and Hfin2 = 14 nm. From this point on, using the same SNC-FinFET with the optimized dimension, varying the temperature from 250 K to 400 K, degrades the RF/analog characteristics while exhibiting the opposite trend for linearity, with improvements of 40.36%, 67.42%, 49.59%, and 62.31% in the 2nd order harmonic, 3rd order harmonic, 2nd order Voltage Intercept Point, and 3rd order Voltage Intercept Point, respectively. The proposed device performance is also analyzed at the circuit level followed by noise margin calculation where at T = 400 K 46.36% of improvement in noise margin is encountered.

Negative capacitance FET based dual-split control 6T-SRAM cell design for energy efficient and robust computing-in memory architectures

A Negative Capacitance Field effet transistor (NCFET) based Dual split control (DSC) 6T-SRAM cell has been designed and explored with Computing-in memory (CiM) architecture for energy efficient demonstration of Deep neural networks (DNN) basic operation such as Input-Weight (Dot) Product. The impact of ferro electric layer thickness (Tfe) on the SRAM cell perfomance metrics such as read noise margin (RNM), write noise margin (WNM) and energy efficiency for read and write operations have been analyzed at supply voltages of 0.3 V and 0.5 V. It has been observed that due to the steep slope characteristics, the NCFET based DSC 6T-SRAM cell design exhibits better RM, WM, and energy efficiency as compared to the baseline CMOS DSC SRAM cell design at VDD = 0.3 V and 0.5 V respectively (with Tfe range of 1 nm to 3 nm). Further, NCFET dual split control scheme for 6T-SRAM cell demonstrate improved read stability and write ability when compared with NCFET 6 T-SRAM cell design along with improved energy efficiency. NCFET based DSC 6T-SRAM CiM cell design has ∼22.77× and 12.41× lower energy consumption compared to the équivalent baseline 40 nm CMOS/baseline SRAM CiM design and ∼ 25.80× and 22.76× lower energy consumption compared to the NCFET based SRAM CiM at VDD = 0.3 V and 0.5 V respectively. NCFETs have improved steep subthreshold slope characteristics at an optimal Tfe value and NCFET SRAM based CiM circuits are expected to have higher noise margins and lower energy consumption compared to the baseline CMOS designs and are effective for NCFET based computing in-memory architectures with reduced read disturb issues in combination with DSC concept.

CNTFET-based SRAM cell design using INDEP technique

As the size of the transistor decreases in the nanoscale regime, certain parameters, such as, cell stability, power dissipation, and delay, have changed. This poses a significant challenge when attempting to scale down metal oxide semiconductor field effect transistor (MOSFET). The carbon nanotube field effect transistor (CNTFET) has exhibited remarkable advantages compared to MOSFETs in circuit designs within the nanoscale range, owing to its extraordinary characteristics. In this work, a CNTFET-based six-transistor (6T) static random access memory (SRAM) cell is designed using the low power input-dependent (INDEP) technique. The suggested circuits' performance and efficiency is enhanced using CNTFET technology. The suggested design undergoes circuit simulations using the 32 nm CNTFET Stanford model. The results obtained from the simulations indicate that the suggested INDEP 6T SRAM cell surpasses both the conventional 6T SRAM cell and the previous designs in terms of power dissipation, delay, and energy efficiency. The hold, read, and write operations use less power, and the hold and write operations take less time to complete. The suggested design also demonstrates improved energy efficiency for hold and read operations compared to the conventional design. Furthermore, a stability analysis is conducted on the suggested INDEP 6T SRAM cell using the static noise margin (SNM) metric. The suggested INDEP approach in comparison to the other schemes has greater SNMs for hold, write, and read operations, indicating improved SRAM cell stability.

Single ended 12T cntfet sram cell with high stability for low power smart device applications

Static random-access memory (SRAM) is the most prevalent type of memory used in current system-on-chips (SOC). SRAMs built using Complementary metal oxide semiconductor (CMOS) transistors, suffer from low stability and significant power dissipation at nano scale regime [1]. Studies show that the Carbon nanotube field effect transistor (CNTFET) are prominent to use at nano scale region. This article proposes a 12T CNTFET SRAM cell and its performance metrics like power, stability and delay are compared with various other recent SRAM cells by simulating them using CNTFETs. Two Schmitt trigger (ST) based cross coupled inverter arrangement make up the storage cell in the suggested 12T CNTFET SRAM bit cell. ST-based inverter has stacked N-type transistors, which reduces the circuit's leakage and the voltage transfer characteristics (VTC) of ST inverter is also sharper than the other conventional inverters, thereby enhancing the stability performance of the proposed bit cell. The cell also uses feedback cutting transistor and a separate read and write path to further improve the stability performances during read and write modes. The suggested 12T CNTFET SRAM cell shows higher write SNM, hold SNM and read SNM when compared to other state of the art SRAM cells. The read and write delay of the proposed 12T CNTFET SRAM cell is also seen to improve in contrast to the other SRAM designs. The proposed 12T CNTFET SRAM cell when simulated using 32 nm CNTFET at 0.9 V, shows write power, hold power, read power, write delay, read delay, write static noise margin (WSNM), HSNM and read static noise margin (RSNM), as 0.19 nW, 1.61 nW, 3.13 µW, 119 pS, 7.33 pS, 444 mV, 420 mV, 420 mV respectively. The suggested cell is also tested for parametric variations and its performance is also recorded. The proposed cell surpasses all other cells considered as far as power and stability are concerned making it suitable for usage in smart devices like smart bands, smart watches etc. A 32 nm Stanford University model is used to simulate the proposed 12T CNTFET SRAM cell using the HSPICE tool.

Novel hybrid-CMOS inverter utilizing phase transition material for enhancing digital logic performance at lower operating voltages

This research paper introduces a novel design for a hybrid-CMOS inverter using vanadium dioxide (VO2), a phase transition material. The proposed inverter exhibits a remarkably steep transition for falling logic at the output(1–0). By leveraging the insulating to metallic current density (IC-IMT) of VO2, the depth and gain of this transition can be finely tuned. Notably, a higher IC-IMT value yields a greater gain in the transition slope. In comparison to a traditional CMOS inverter, the designed inverter demonstrates several advantages. It achieves higher values of lower noise margin (NML) and significantly reduces static power dissipation by 97.7%. These promising outcomes present an exciting opportunity for designing inverters at lower drain voltages, especially in devices operating at lower technology nodes. Furthermore, the hybrid-CMOS inverter is designed to excel in the sub-threshold region of operation, resulting in elevated values of lower noise margin and reduced leakage current values.

Performance investigation of stacked-channel junctionless Tri-Gate FinFET 8T-SRAM cell

Junctionless FinFET devices are a substitute for conventional FinFET devices due to their short channel effects and easy manufacturing at sub 22 nm technology node. The manuscript presents an 8T-SRAM cell based on tri-gate junctionless FinFET technology. The FinFET device is designed with source/drain of Si material and the channel as a stack of Si − Si 0.75 Ge 0.25 − Si. The proposed SRAM cell structure consists of a CMOS inverter with stacked p-FinFETs, improving its performance in terms of noise margin and leakage power consumption. The manuscript investigates the variation of Static Noise Margin (SNM), leakage power dissipation and delay with supply voltage to analyze the sub-threshold operation of SRAM cell. The results reveal that the cascaded p-FinFETs minimize the leakage current owing to the stack effect, resulting in improved noise margin and lower leakage power. The stacked p-FinFET devices based SRAM cell achieves 1.11x read noise margin, 1.11x hold noise margin, −1.08x write noise margin and 57.1% less leakage power compared to conventional SRAM cell at 1.0 V. However, it exhibits more delay due to increased resistance and capacitance of the cascaded transistors. The process variation analysis is also performed to investigate the SNM distribution using monte-carlo simulation by taking 10,000 samples. The results indicate that the SRAM cell structures provide higher than 6σ yield at range of supply voltages.

Inverter and Universal Gates Implementation Using Novel Core Insulator Double Gate (CIDG) MOSFETs

The Core Insulator Double Gate (CIDG) MOSFET has been explored for digital applications in which the presence of core insulator diminishes the bulk conduction and reduces the off state current. The drain currents of n- and p-type CIDG MOSFETs are matched by tuning gate work functions to deliver the symmetrical pull-up and pull-down characteristics. The inverter and universal logic gates (NAND and NOR) have been designed and implemented to show the usability of the CIDG MOSFETs for digital applications. The DC and transient characteristic of the inverter along with Static Noise Margin (SNM) and time delay parameters have been examined. The designed Inverter shows steeper voltage transfer characteristics, reduced short circuit power dissipation and improved noise immunity. The CIDG MOSFET based NAND and NOR gate implementation and validation by transient analysis have been shown for the first time to the best knowledge of the authors. Also, the rise and fall times of the inverter, NAND and NOR gates have been found to be improved as compared to the DG MOSFET counterparts. The present analysis establishes that CIDG MOSFETs are useful in designing digital circuits with improved performance.

A CNTFET based stable, single-ended 7T SRAM cell with improved write operation

Many researchers are working to improve the write operation in SRAM bit-cell for better write stability, low power dissipation, and minimal access time during the write process. However, the read and hold operation parameters should not be compromised to achieve these improvements. This paper presents a stable single-ended seven-carbon nanotube field-effect transistor (CNTFET) driven SRAM cell with improved write operation. The one-side inverter weakening approach for write and transistor decoupling for read operation leads to reduced dynamic power, low write delay, reduced leakage power, and improved stability. The proposed design is compared with conventional 6T (Conv6T) and three recently proposed designs, i.e., feedback-cutting 8T (feed-cut 8T), Low-power 8T and low-leakage 7T cell. The write delay and write PDP of the proposed design improve by 4.05×/3.58×/1.19×/1.21×and 11.11×/24.71×/2.96×/3.32×, respectively, compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. Also, the read delay and read PDP of the proposed design improve by 1×/1.03×/1.72×/1.56× and 1×/1.03×/1.82×/1.77×, respectively, compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. The leakage power of the proposed design is reduced by 1.08×/1.84×/0.46×/0.72× compared to Conv6T/feed-cut 8T/ low-power 8T/ low-leakage 7T. The noise margin of the proposed cell for hold/write/read operation is improved by 1.02×/1.05×/0.99×compared to the Conv6T design. The simulation was performed using Stanford University’s 32 nm CNTFET model on the cadence virtuoso platform.

Low power CNTFET-based ternary multiplier for digital signal processing applications

Abstract Multiplication is a fundamental arithmetic process, although it necessitates more hardware resources. Researchers in advanced technology attempted to boost the speed and lower the power in digital signal processing applications by utilizing multipliers. The majority of digital signal processing applications demanded increased speed. In addition, ternary logic based on CNTFETs is a feasible alternative for Si-MOSFETs. The article proposes a ternary multiplier, which is designed using proposed ternary logical and combinational circuits that includes STI, TNAND, TNOR, and ternary decoder. The proposed and existing designs are simulated, compared, and analysed on the parameters of delay, average power, and noise using the HSPICE simulator. Therefore, the results show 10%, 81% and 81% improvement in delay, average power, and PDP respectively for proposed TMUL. The noise margin of the proposed TMUL is increased up to 54% over existing circuits. The proposed TDecoder, STI, TNAND, and TNOR are 95%, 97%, 81%, and 95% more energy efficient than existing designs, respectively.

Quantum and classical simulation of core shell based junctionless field effect transistor with digital application

The detailed performance analysis of core–shell Gate All Around junctionless field effect transistor along with CMOS inverter as an application with quantum models is presented in this paper for the first time. To appreciate the performance of the device and the application even at smaller channel length, the comparison with classical models is also presented. The OFF current was calculated as 3.68 × 10−16A on incorporating the quantum models. The subthreshold swing (SS) and Drain induced barrier lowering (DIBL) are found to be near ideal values. The SS and DIBL was calculated as 62.82 mV/dec and 33.4 mV/V. The DIBL was found to be lesser by 52.82% with quantum model than classical model. The performance obtained using quantum models are better than the classical models in terms of different parameters such as OFF current, ON current, SS, DIBL, threshold voltage, transconductance. Further, the performance of the CMOS inverter with quantum models by considering the n-type and p-type core–shell Gate All Around junctionless field effect transistor is also presented . The OFF current of p-type and n-type was matched before designing the application. A sharp transfer characteristics of the CMOS inverter is obtained. The performance was also studied by calculating the drain current from each of p-type and n-type and found to be more than 1 × 10−7A and SNM (Static Noise Margin) was calculated as 267 mV. The transient response of CMOS inverter exhibits the potential of CMOS inverter using the proposed device even at smaller channel lengths.

Ultraflexible Monolithic Three-Dimensional Static Random Access Memory.

Flexible static random access memory (SRAM) plays an important role in flexible electronics and systems. However, achieving SRAM with a small footprint, high flexibility, and high thermal stability has always been a big challenge. In this work, an ultraflexible six-transistor SRAM with high integration density is realized based on a monolithic three-dimensional (M3D) design. In this design, vertical stacked n-type indium gallium zinc oxide thin film transistors and p-type carbon nanotube transistors share common gate and drain electrodes, respectively, saving interlayer vias used in traditional M3D designs. This compact architecture reduces the footprint of the SRAM cell from a six-transistor to a four-transistor area, saving 33% of the area, and significantly enables the SRAM to have the highest flexibility among the reported ones, withstanding a harsh deforming process (6000 cycles of bending at a radius of 500 μm) without performance degradation. Moreover, this design facilitates the thermal stability of the SRAM under high temperature (333 K). It also exhibits great static and dynamic performance, with the highest normalized hold noise margin of 73.6%, a maximum gain of 151.2, and a minimum static power consumption of 3.15 μW in hold operation among the reported flexible SRAMs. This demonstration provides possibilities for SRAMs to be used in advanced wearable system applications.

IMPACT OF SUPPLY VOLTAGE ON SRAM CELL POWER DISSIPATION UNDER DIFFERENT TOPOLOGIES

The high storage density and quick access times of Static Random Access Memory (SRAM) make it a critical component of many Very Large Scale Integration circuits. However, device scaling in today's technology leads to an increase in dynamic power and a decrease in noise margin, posing significant challenges to memory circuit design for the next generation of devices. In addition, sub-threshold leakage is also a concern. In recent years, the increasing demand for notebooks, laptops, IC memory cards, and mobile communication devices has driven the development of low-power, low-voltage memory circuits. Static Random Access Memoryis widely used as on-chip and off-chip memory for portable applications because they are easy to use and have minimal standby leakage. Since 60% to 70% of the chip memory is used, SRAM optimization is the focus of research. The SRAM cell's architecture and performance have been studied using various technologies to minimize power dissipation while maintaining stability. Based on the power dissipation, including static and dynamic power dissipation, and Static Noise Margin (SNM), the SRAM cell performance is compared with different topologies. The SNM fluctuation is considered along with the variation of supply voltage.