IMPACT OF SUPPLY VOLTAGE ON SRAM CELL POWER DISSIPATION UNDER DIFFERENT TOPOLOGIES

Abstract

The high storage density and quick access times of Static Random Access Memory (SRAM) make it a critical component of many Very Large Scale Integration circuits. However, device scaling in today's technology leads to an increase in dynamic power and a decrease in noise margin, posing significant challenges to memory circuit design for the next generation of devices. In addition, sub-threshold leakage is also a concern. In recent years, the increasing demand for notebooks, laptops, IC memory cards, and mobile communication devices has driven the development of low-power, low-voltage memory circuits. Static Random Access Memoryis widely used as on-chip and off-chip memory for portable applications because they are easy to use and have minimal standby leakage. Since 60% to 70% of the chip memory is used, SRAM optimization is the focus of research. The SRAM cell's architecture and performance have been studied using various technologies to minimize power dissipation while maintaining stability. Based on the power dissipation, including static and dynamic power dissipation, and Static Noise Margin (SNM), the SRAM cell performance is compared with different topologies. The SNM fluctuation is considered along with the variation of supply voltage.