Single ended 12T cntfet sram cell with high stability for low power smart device applications

Abstract

Static random-access memory (SRAM) is the most prevalent type of memory used in current system-on-chips (SOC). SRAMs built using Complementary metal oxide semiconductor (CMOS) transistors, suffer from low stability and significant power dissipation at nano scale regime [1]. Studies show that the Carbon nanotube field effect transistor (CNTFET) are prominent to use at nano scale region. This article proposes a 12T CNTFET SRAM cell and its performance metrics like power, stability and delay are compared with various other recent SRAM cells by simulating them using CNTFETs. Two Schmitt trigger (ST) based cross coupled inverter arrangement make up the storage cell in the suggested 12T CNTFET SRAM bit cell. ST-based inverter has stacked N-type transistors, which reduces the circuit's leakage and the voltage transfer characteristics (VTC) of ST inverter is also sharper than the other conventional inverters, thereby enhancing the stability performance of the proposed bit cell. The cell also uses feedback cutting transistor and a separate read and write path to further improve the stability performances during read and write modes. The suggested 12T CNTFET SRAM cell shows higher write SNM, hold SNM and read SNM when compared to other state of the art SRAM cells. The read and write delay of the proposed 12T CNTFET SRAM cell is also seen to improve in contrast to the other SRAM designs. The proposed 12T CNTFET SRAM cell when simulated using 32 nm CNTFET at 0.9 V, shows write power, hold power, read power, write delay, read delay, write static noise margin (WSNM), HSNM and read static noise margin (RSNM), as 0.19 nW, 1.61 nW, 3.13 µW, 119 pS, 7.33 pS, 444 mV, 420 mV, 420 mV respectively. The suggested cell is also tested for parametric variations and its performance is also recorded. The proposed cell surpasses all other cells considered as far as power and stability are concerned making it suitable for usage in smart devices like smart bands, smart watches etc. A 32 nm Stanford University model is used to simulate the proposed 12T CNTFET SRAM cell using the HSPICE tool.