Network-on-Chip Research Articles

A Review Paper on Multi-tasking on Network on Chip(NOC)

Now a days development of Integrated Circuit technology is composed of multiple cores in a single chip called System on Chip (SoC). The technology has advanced from to single to multi core so as to improve the performance. These require effective communication, High performance, flexibility, scalability and design friendly interconnection. Before the initiation of Network on Chip (NoC), interconnection is based on wire and they cannot encounter ever increasing demand for on chip systems due to lack of scalability. NoC has several advantages such as high bandwidth, low power consumption and scalability. The interconnection among multiple cores on a chip have impact on communication and performance of chip design in terms of collision occurrence, noise, and pocket loss ratio and delay. Therefore, it is valuable studying the different multitasking algorithms. This paper reviews the widespread NoC algorithms and also few recent inclinations in interconnection networks. The area, power consumption, design complexity and congestion are studied to review the performance and summarize their merits.

Built-in Self-prevention (BISP) for runtime ageing effects of TSVs in 3D ICs

The adoption of Through-Silicon-Vias (TSVs) in Three-Dimensional Integrated Circuits (3D ICs) is gaining momentum in the industry, thanks to the numerous advantages it offers over traditional 2D ICs. However, TSVs are susceptible to defects during their formation, die stacking, and operational lifespan, leading to reliability issues in 3D ICs. While existing approaches have focused on addressing assembly and stacking yield losses, the runtime failure caused by Electro-migration (EM) remains a significant challenge in commercializing TSV-based 3D ICs. Detecting and monitoring TSV defects require an expensive on-chip sensor network, making it crucial to implement a cost-effective TSV defect prevention and detection scheme. This paper introduces a runtime Built-in Self-prevention (BISP) scheme that significantly extends TSV lifetime. The proposed method employs a repair circuit to rectify post-manufacturing TSV defects, resulting in minimal hardware costs. Furthermore, the combined repair and prevention solution introduces a delay overhead of less than 0.5 ns, ensuring compliance with timing constraints.

Time-domain photonic image processor based on speckle projection and reservoir computing

High-speed image processing is essential for many real-time applications. On-chip photonic neural network processors have the potential to speed up image processing, but their scalability is limited in terms of the number of input/output channels because high-density integration is challenging. Here, we propose a photonic time-domain image processing approach, where real-world visual information is compressively acquired through a single input channel. Thus, large-scale processing is enabled even when using a small photonic processor with limited input/output channels. The drawback of the time-domain serial operation can be mitigated using ultrahigh-speed data acquisition based on gigahertz-rate speckle projection. We combine it with a photonic reservoir computer and demonstrate that this approach is capable of dynamic image recognition at gigahertz rates. Furthermore, we demonstrate that this approach can also be used for high-speed learning-based imaging. The proposed approach can be extended to diverse applications, including target tracking, flow cytometry, and imaging of sub-nanosecond phenomena.

ObNoCs : Protecting Network-on-Chip Fabrics Against Reverse-Engineering Attacks

Modern System-on-Chip designs typically use Network-on-Chip (NoC) fabrics to implement coordination among integrated hardware blocks. An important class of security vulnerabilities involves a rogue foundry reverse-engineering the NoC topology and routing logic. In this paper, we develop an infrastructure, ObNoCs , for protecting NoC fabrics against such attacks. ObNoCs systematically replaces router connections with switches that can be programmed after fabrication to induce the desired topology. Our approach provides provable redaction of NoC functionality: switch configurations induce a large number of legal topologies, only one of which corresponds to the intended topology. We implement the ObNoCs methodology on Intel Quartus™ Platform, and experimental results on realistic SoC designs show that the architecture incurs minimal overhead in power, resource utilization, and system latency.

Efficient application mapping approach based on grey wolf optimization for network on chip

In modern chip designs with multiple processors, network-on-chip (NoC) has emerged as a critical solution, offering scalability, flexibility, modularity, and efficiency. However, a significant challenge in application mapping is minimizing communication costs as they directly affect performance and energy consumption. Although several mapping algorithms have been developed, they often suffer from complexity, suboptimal performance, and slow convergence. To address these challenges, this paper proposes a novel approach for mapping using the grey wolf optimization (GWO) technique inspired by nature. The proposed GWO-based mapping approach for NoC (GNoC) is augmented with an effective clustering-based initial mapping strategy, further enhancing its capabilities. Furthermore, a second heuristic algorithm is introduced, incorporating a modified GWO method with polynomial regression (GNoC-PR). This modification optimizes the runtime efficiency and enhances the overall mapping quality. The proposed method was evaluated through comprehensive simulations and compared with state-of-the-art solutions. The results demonstrate that the proposed algorithm outperforms existing methods in several key metrics, including a power consumption reduction of 19.7%, energy efficiency improvement of 17%, and a significant 40% decrease in computational overhead on average. To validate the effectiveness of our mapping technique, we evaluated both embedded and synthetic applications, considering various metrics such as communication cost, average network latency, and power consumption.

Address Obfuscation to Protect against Hardware Trojans in Network-on-Chips

In modern computing, which relies on the interconnection of networks used in many/multi-core systems, any system can be critically subverted if the interconnection is compromised. This can be done in a multitude of ways, but the threat of a hardware Trojan (HT) being injected into a system is particularly prevalent due to the increase in third-party manufacturers for system-on-chip (SoC) designs. With a local injection of an HT in an SoC, an adversary can gain access to information about applications running on the system by revealing specific communications of the SoC, and the network-on-chip (NoC) as a whole. This heavily compromises the system and gives information to the attacker, which can lead to more tailored, compromising attacks. In this paper, we demonstrate an HT that exploits communication patterns inside an SoC to reveal applications that are running on an NoC with multi/many-core processors. This is performed by leaking packet counts, after which the attacker then uses machine learning techniques to identify applications running on processors, and the SoC as a whole. We also propose a LUT-based obfuscation technique to limit the information available to the hardware Trojan. Our results indicate that this obfuscation method can reduce the accuracy of this attack from 99% to <8% in multi/many-core systems.

A Deep Learning Network-on-Chip (NoC)-Based Switch-Router to Enhance Information Security in Resource-Constrained Devices

In a resource-constrained environment of the 21st century, the use of hardware-based reconfigurable systems such as Field Programmable Gate Array (FPGAs) is considered an effective way to enhance information security. In comparison with traditional custom circuitry that does not give a flexible approach, it is observed that the reconfigurable hardware shows an excellent potential for cyber security by increasing hardware speeds and flexibility. Therefore, in a quest to integrate multi-core systems, the Network-on-Chip (NoC) has become one of the popular widespread techniques to maximize router security. Due to the significant overhead of chip space and the power consumption of the routers, it is substantially more expensive to construct as compared to a bus-based system. The control component (CC) interacts with the networks that inject packets based on router switching and activity. These control components are coupled with each network to produce a system of controlled networks. The system is further linked with CFM or a Centralized Fabric Manager, which serves as the network’s focal point. After that, the CFM runs the algorithm regularly. The analytic parameters comprise flip flop, power, latency, number of lookup tables (LUTs), and throughput. In the proposed method, the number of LUTs is [Formula: see text], the flip flop is [Formula: see text], the power is [Formula: see text]W, the latency is 5941[Formula: see text]ns, and the planned throughput is 0.56 flits/cycle. Results indicate that the crossbar switch reduces errors and minimizes the delay in the architecture’s outcome level, which further overcomes the descriptions of performance, power throughput, and area delay parameters. The findings of the research can be useful to enhance information security among lightweight devices besides minimizing the chances of network attacks in today’s dynamic and complex cyberspace.

Design and Implementation of High QoS 3D-NoC using Modified Double Particle Swarm Optimization on FPGA

One technique to overcome the exponential growth bottleneck is to increase the number of cores on a processor, although having too many cores might cause issues including chip overheating and communication blockage. The problem of the communication bottleneck on the chip is presently effectively resolved by networks-on-chip (NoC). A 3D stack of chips is now possible, thanks to recent developments in IC manufacturing techniques, enabling to reduce of chip area while increasing chip throughput and reducing power consumption. The automated process associated with mapping applications to form three-dimensional NoC architectures is a significant new path in 3D NoC research. This work proposes a 3D NoC partitioning approach that can identify the 3D NoC region that has to be mapped. A double particle swarm optimization (DPSO) inspired algorithmic technique, which may combine the characteristics having neighbourhood search and genetic architectures, also addresses the challenge of a particle swarm algorithm descending into local optimal solutions. Experimental evidence supports the claim that this hybrid optimization algorithm based on Double Particle Swarm Optimisation outperforms the conventional heuristic technique in terms of output rate and loss in energy. The findings demonstrate that in a network of the same size, the newly introduced router delivers the lowest loss on the longest path. Three factors, namely energy, latency or delay, and throughput, are compared between the suggested 3D mesh ONoC and its 2D version. When comparing power consumption between 3D ONoC and its electronic and 2D equivalents, which both have 512 IP cores, it may save roughly 79.9% of the energy used by the electronic counterpart and 24.3% of the energy used by the latter. The network efficiency of the 3D mesh ONoC is simulated by DPSO in a variety of configurations. The outcomes also demonstrate an increase in performance over the 2D ONoC. As a flexible communication solution, Network-On-Chips (NoCs) have been frequently employed in the development of multiprocessor system-on-chips (MPSoCs). By outsourcing their communication activities, NoCs permit on-chip Intellectual Property (IP) cores to communicate with one another and function at a better level. The important components in assigning application duties, distributing the work to the IPs, and coordinating communication among them are mapping and scheduling methods. This study aims to present an entirely advanced form of research in the area of 3D NoC mapping and scheduling applications, grouping the results according to various parameters and offering several suggestions for further research.

Clock tree generation by abutment in synchoros VLSI design

Synchoros VLSI design style has been proposed as an alternative to standard cell-based design. Standard cells are replaced by synchoros, large grain, VLSI design objects called SiLago (Silicon Lego) blocks. This new design style eliminates the need to synthesise ad hoc wires of any type: functional and infrastructural. SiLago blocks are organised into region instances. In a region instance, communication amongst SiLago blocks is synchronous and happens over a regional network on chip (NoC), whose fragments are also absorbed into SiLago blocks. Consequently, the regional NoCs get created by the abutment of SiLago blocks. The clock tree used in a region is called a regional clock tree (RCT). The synchoros VLSI design style requires that the RCT, like the regional NoCs, is also created by abutting its fragments. The RCT fragments are absorbed within the SiLago blocks. The RCT created by the abutment is not an ad-hoc clock tree but a structured and predictable design with known cost metrics. The design of such an RCT is the focus of this paper. The scheme is scalable, and we demonstrate that the proposed RCT can be generated for valid VLSI designs of ∼1.5 million gates. The RCT created by abutment is correct by construction, and its properties are predictable. Additionally, we present an in-depth description of the method used to find the optimal configuration for the proposed design. We have validated the generated RCTs with static timing analysis to validate the correct-by-construction claim. Finally, we show that the cost metrics of the SiLago RCT is comparable to the one generated by commercial EDA tools.

Integrated Bragg grating filters based on silicon-Sb2Se3 with non-volatile bandgap engineering capability.

Integrated optical filters show outstanding capability in integrated reconfigurable photonic applications, including wavelength division multiplexing (WDM), programmable photonic processors, and on-chip quantum photonic networks. Present schemes for reconfigurable filters either have a large footprint or suffer from high static power consumption, hindering the development of reconfigurable photonic integrated systems. Here, a reconfigurable hybrid Bragg grating filter is elaborately designed through a precise, modified coupling mode theory. It is also experimentally presented by integrating non-volatile phase change material (PCM) Sb2Se3 on silicon to realize compact, low-loss, and broadband engineering operations. The fabricated filter holds a compact footprint of 0.5 µm × 43.5 µm and maintains a low insertion loss of < 0.5 dB after multiple levels of engineering to achieve crystallization. The filter is able to switch from a low-loss transmission state to the Bragg reflection state, making it a favorable solution for large-scale reconfigurable photonic circuits. With a switching extinction ratio over 30 dB at 1504.85 nm, this hybrid filter breaks the tradeoff between insertion loss and tuning range. These results reveal its potential as a new candidate for a basic element in large-scale non-volatile reconfigurable systems.

An improved reconfiguration algorithm for handling 1-point NoC failures

In today’s world, the demands for high-performance computing necessitate faster on-chip communication. Current chips with a large number of on-chip elements need an efficient alternative such as network-on-chip (NoC) for on-chip communication. As technology down scales toward the deep sub-micron, process variability makes the transistors more unreliable. Hence, on-chip elements including NoC can suffer from permanent/transient failures. In an NoC, 1-link/1-router failure can disrupt overall connectivity. The paper presents an improved routing reconfiguration algorithm for handling all 1-point permanent failures in 2D mesh NoC. By 1-point failure, we mean a failure can be occurred on any network link/router. State-of-the-art approaches either require a large number of reconfiguration cycles or provide partial support for 1-point failures, i.e., cover only 1-link failures. Proposed approach performs partial reconfiguration of routing function implemented using logic-bits instead of costly routing tables, thus reducing hardware overheads for larger networks as well. In terms of performance, the average flit latency cycles are reduced up to 31% and the average network throughput is improved up to 14.5% for 1-router failure in 8 × 8 2D mesh NoC. For 2-router failures, the improvements are 20% and 13% in terms of average flit latency cycles and average network throughput, respectively.

An Overview on On-chip Network Routing Optimisation

As the number of cores in multi-core systems increases, bus-based systems face significant challenges in terms of scalability, average transmission latency and power consumption. In this context, on-chip networks emerged as a suitable communication architecture for System On Chip (SoC) based entirely on the communication ideas in computer networks and taking into account the characteristics of the system on chip in SoCs. With the introduction of on-chip networks, related research has been developed, such as on-chip network topology, communication quality of service, on-chip network routing algorithms, and on-chip network fault tolerance. He then introduces on-chip network routing algorithms and fault-tolerant routing algorithms from different perspectives, and finally points out the directions of fault-tolerant routing algorithms worthy of research.

PaST-NoC: A Packet-Switched Superconducting Temporal NoC

Temporal computing promises to mitigate the stringent area constraints and clock distribution overheads of traditional superconducting digital computing. To design a scalable, area- and power-efficient superconducting network on chip (NoC), we propose packet-switched superconducting temporal NoC (PaST-NoC). PaST-NoC operates its control path in the temporal domain using race logic (RL), combined with bufferless deflection flow control to minimize area. Packets encode their destination using RL and carry a collection of data pulses that the receiver can interpret as pulse trains, RL, serialized binary, or other formats. We demonstrate how to scale up PaST-NoC to arbitrary topologies based on 2x2 routers and 4x4 butterflies as building blocks. As we show, if data pulses are interpreted using RL, PaST-NoC outperforms state-of-the-art superconducting binary NoCs in throughput per area by as much as 5x for long packets.

Adaptive Machine Learning-Based Proactive Thermal Management for NoC Systems

Because of the high-complex interconnection in contemporary multicore systems, the network-on-chip (NoC) technology has been proven as an efficient way to solve the communication problem in multicore systems. However, the thermal problem becomes the main design challenge in the current NoC systems due to the high-diverse workload distribution and large power density. Therefore, proactive dynamic thermal management (PDTM) is employed as an efficient way to control the system temperature. Based on the predicted temperature information, the PDTM can control the system temperature in advance to reduce the performance impact during the temperature control period. However, conventional temperature prediction models are usually built based on specific physical parameters, which are usually temperature-sensitive. Consequently, the current temperature prediction models still result in significant temperature prediction errors. To solve this problem, a novel adaptive machine learning (ML)-based PDTM is proposed in this work. The adaptive ML-based PDTM first uses an adaptive single layer perceptron (ASLP), which is composed of a single-neuron operation and a least mean square (LMS) adaptive filter technology, to precisely predict the future temperature. Afterward, the proposed adaptive reinforcement learning (RL) is used to find the proper throttling ratio to control the system temperature. In this way, the proposed adaptive ML-based PDTM can adapt to the hyperplane of the temperature behavior of the NoC system and provide a proper temperature control strategy at runtime. Compared with related works, the proposed approach reduces average temperature prediction error by 0.2%–78.0% and improves the system performance by 2.4%–43.0% with smaller hardware overhead.

On chip optical neural networks based on MMI microring resonators for image classification

We propose a new on-chip optical neural network (OONN) based on multimode interference-microring resonators (MMI-RRs). The suggested structure eliminates the need for wavelength division multiplexers (WDM) to create an optical neuron on a single chip. New microring resonator structure based on 4×4 MMI coupler with a size of 24µm × 2900 µm is used for the basic elements of the computation matrix, as a result a higher bandwidth and free spectral range (FSR) can be achieved. The Si3N4 platform along with the graphene sheet is designed to modulate the signals and weights of the neural networks at a very high speed. The Si3N4 can provide wide range of operating wavelengths and can work directly with the wavelengths of color images. The structure's benefits include rapid computing speed, little loss, and the ability to handle both positive and negative values. The OONN has been applied to the MNIST dataset with a speed faster than 2.8 to 14x times compared with the conventional GPU methods.

Improving power and performance of on-chip network through virtual channel sharing and power gating

Networks-on-Chip (NoCs) are becoming the communication backbone in multicore chips. The router buffer holds a critical significance for the communication performance of NoC. However, the bursty traffic means that the buffers are idle for many periods and generate a significant amount of static power. Moreover, due to the uneven traffic distribution, some buffers within the router stand idle even at network saturation. Both the performance and power budget of NoC heavily depends on the router’s buffer budget. Therefore, we desperately demand a mechanism to maximize the usage of idle buffers to balance the load and improve the performance ceiling of NoC. Dynamically based on network traffic, early switching on or off of buffers to save power consumption. We propose a modified microarchitecture of the virtual channel sharing router, MVCR. The MVCR innovatively applies aggressive fine-grained power gating mechanisms to the idle buffers of each directional input port (east, west, south, and north) to achieve static power savings. Moreover, the MVCR further extends the sleeping VC period through an efficient packet-transmission adjustment mechanism, thus achieving maximum static power savings and improved network performance. Synthetic applications and real benchmarks have been used to validate MCVR. Compared to traditional router scheme, MVCR increases throughput by 30%, reduces power consumption by 47%, and has a latency overhead of about 6%. The key performance metrics are better than other solutions, and the added area cost is moderate.

7 [formula omitted]J/inference end-to-end gesture recognition from dynamic vision sensor data using ternarized hybrid convolutional neural networks

Dynamic vision sensor (DVS) cameras enable energy-activity proportional visual sensing by only propagating events produced by changes in the observed scene. Furthermore, by generating these events asynchronously, they offer μs-scale latency while eliminating the redundant data transmission inherent to classical, frame-based cameras. However, the potential of DVS to improve the energy efficiency of IoT sensor nodes can only be fully realized with efficient and flexible systems that tightly integrate sensing, processing, and actuation capabilities. In this paper, we propose a complete end-to-end pipeline for DVS event data classification implemented on the Kraken parallel ultra-low power (PULP) system-on-chip and apply it to gesture recognition. A dedicated on-chip peripheral interface for DVS cameras aggregates the received events into ternary event frames. We process these video frames with a fully ternarized two-stage temporal convolutional network (TCN). The neural network can be executed either on Kraken’s PULP cluster of general-purpose RISC-V cores or on CUTIE, the on-chip ternary neural network accelerator. We perform extensive ablations on network structure, training, and data generation parameters. We achieve a validation accuracy of 97.7% on the DVS128 11-class gesture dataset, a new record for embedded implementations. With in-silicon power and energy measurements, we demonstrate a classification energy of 7 μJ at a latency of 0.9ms when running the TCN on CUTIE, a reduction of inference energy by 67× when compared to the state of the art in embedded gesture recognition. The processing system consumes as little as 4.7mW in continuous inference, enabling always-on gesture recognition and closing the gap between the efficiency potential of DVS cameras and application scenarios.

A Performance Constrained Metaheuristic Algorithm for 2D Mesh Based NoC

Integrating large number of Intellectual Property (IP) cores onto a single chip has been made possible with the technology scaling and shrinking in the size of transistors. This has led designers to create a scalable and flexible on-chip network infrastructure – Network on Chip (NoC). Mapping application graphs on multiple cores of NoC architecture is one of the challenging research problems. The all in all performance of NoC network depends primarily on an efficient and cost-effective mapping technique which optimizes several performance metrics. These metrics primarily consists of communication cost, energy, throughput, latency, power dissipation and simulation time. A metaheuristic state-of-the-art nature inspired mapping approach for NoC's called Hunger Games Search Algorithm (HGSA) has been introduced in this research work. The devised algorithm minimizes NoC energy and power consumption based on six standard available embedded application benchmarks. Experimental results demonstrate that the presented technique outperforms as compared to other existing nature-inspired meta-heuristic application mapping approaches.

Implementation of energy-efficient convolutional neural networks based on kernel-pruned silicon photonics.

Silicon-based optical neural networks offer the prospect of high-performance computing on integrated photonic circuits. However, the scalability of on-chip optical depth networks is restricted by the limited energy and space resources. Here, we present a silicon-based photonic convolutional neural network (PCNN) combined with the kernel pruning, in which the optical convolutional computing core of PCNN is a tunable micro-ring weight bank. Our numerical simulation demonstrates the effect of weight mapping accuracy on PCNN performance and we find that the performance of PCNN decreases significantly when the weight mapping accuracy is less than 4.3 bits. Additionally, the experimental demonstration shows that the accuracy of the PCNN on the MNIST dataset has a slight loss compared to the original CNN when 93.75 % of the convolutional kernels are pruned. By making use of kernel pruning, the energy saved by a convolutional kernel removal is about 202.3 mW, and the overall energy saved has a linear relationship with the number of kernels removed. The methodology is scalable and provides a feasible solution for implementing faster and more energy-efficient large-scale optical convolutional neural networks on photonic integrated circuits.

TNT: A Modular Approach to Traversing Physically Heterogeneous NOCs at Bare-wire Latency

The ideal latency for on-chip network traversal would be the delay incurred from wire traversal alone. Unfortunately, in a realistic modular network, the latency for a packet to traverse the network is significantly higher than this wire delay. The main limiter to achieving lower latency is the modular quantization of network traversal into hops. Beyond this, the physical heterogeneity in real-world systems further complicate the ability to reach ideal wire-only delay. In this work, we propose TNT or Transparent Network Traversal . TNT targets ideal network latency by attempting source to destination network traversal as a single multi-cycle ‘long-hop’, bypassing the quantization effects of intermediate routers via transparent data/information flow. TNT is built in a modular tile-scalable manner via a novel control path performing neighbor-to-neighbor interactions but enabling end-to-end transparent flit traversal. Further, TNT’s fine grained on-the-fly delay tracking allows it to cope with physical NOC heterogeneity across the chip. Analysis on Ligra graph workloads shows that TNT can reduce NOC latency by as much as 43% compared to the state of the art and allows efficiency gains up to 38%. Further, it can achieve more than 3x the benefits of the best/closest alternative research proposal, SMART [ 43 ].