Built-in Self-prevention (BISP) for runtime ageing effects of TSVs in 3D ICs

Abstract

The adoption of Through-Silicon-Vias (TSVs) in Three-Dimensional Integrated Circuits (3D ICs) is gaining momentum in the industry, thanks to the numerous advantages it offers over traditional 2D ICs. However, TSVs are susceptible to defects during their formation, die stacking, and operational lifespan, leading to reliability issues in 3D ICs. While existing approaches have focused on addressing assembly and stacking yield losses, the runtime failure caused by Electro-migration (EM) remains a significant challenge in commercializing TSV-based 3D ICs. Detecting and monitoring TSV defects require an expensive on-chip sensor network, making it crucial to implement a cost-effective TSV defect prevention and detection scheme. This paper introduces a runtime Built-in Self-prevention (BISP) scheme that significantly extends TSV lifetime. The proposed method employs a repair circuit to rectify post-manufacturing TSV defects, resulting in minimal hardware costs. Furthermore, the combined repair and prevention solution introduces a delay overhead of less than 0.5 ns, ensuring compliance with timing constraints.