Network-on-Chip Research Articles

BΔ-NIS: Performance analysis of an efficient data compression technique for on-chip communication network

Nowadays, system-on-chip (SoC) integrates more processing cores and IPs with network-on-chip (NoC) for satisfying today's demands, including low power consumption and high performance, without affecting the elasticity and scalability. When the on-chip processing elements (PEs) are increased, burst traffic will be generated from memory and cache accesses. As a result, the packet transmission latency is increased, reducing the system's speed performance. This paper proposes a new hybrid Base delta Neighbourhood Indexing Sequence (BΔ-NIS) based compression method for compressing the network traffic. The previous solutions for data compression often contain incompressible packets for certain data patterns. The proposed method uses Neighbourhood Indexing Sequence (NIS) algorithm to determine the optimal codeword for uncompressible chunks of delta compression approach using zeros and ones based traversals. Because of the dynamic nature of BΔ-NIS, it is highly effective and compresses all chunks in the packets efficiently. Moreover, the concept of dynamic header flit extension is introduced in the proposed compression method, which provide unlimited scalability. The proposed BΔ-NIS algorithm is robust to packet losses and leads to significant power saving. The simulation results show that the proposed BΔ-NIS reduces the hardware overhead and overtakes the existing data compression techniques by attaining a mean compression ratio of 0.73. In addition, BΔ-NIS accomplishes 51% latency reduction compared to the baseline router (without any compression). It also minimizes the power consumption of the de/compression modules by 70.14% and 20.8% as compared to the NoΔ and FlitZip respectively.

Silicon photonic architecture for training deep neural networks with direct feedback alignment

There has been growing interest in using photonic processors for performing neural network inference operations; however, these networks are currently trained using standard digital electronics. Here, we propose on-chip training of neural networks enabled by a CMOS-compatible silicon photonic architecture to harness the potential for massively parallel, efficient, and fast data operations. Our scheme employs the direct feedback alignment training algorithm, which trains neural networks using error feedback rather than error backpropagation, and can operate at speeds of trillions of multiply–accumulate (MAC) operations per second while consuming less than one picojoule per MAC operation. The photonic architecture exploits parallelized matrix–vector multiplications using arrays of microring resonators for processing multi-channel analog signals along single waveguide buses to calculate the gradient vector for each neural network layerin situ. We also experimentally demonstrate training deep neural networks with the MNIST dataset using on-chip MAC operation results. Our approach for efficient, ultra-fast neural network training showcases photonics as a promising platform for executing artificial intelligence applications.

Design of a high-performance router with distributed shared-buffer for load balancing for on-chip networks

Design of a high-performance router with distributed shared-buffer for load balancing for on-chip networks

Congestion aware and game based odd even adaptive routing in network on chip many-core architecture

The era of single processors had almost reached a saturation state, and the industry had moved to multi-core processors for the newer generation of many-core architecture. Interconnections between multiple cores with network on chip (NoC) surpass traditional bus architecture for its quality of service (QoS) and other additional services. Seamless communication among the cores is more significant for better performance and the proper utilization of the cores. The rise in the cores count in a semiconductor chip adds the complexity of the communication among cores. Cache misses request and packet transmission’s traffic possibly will reduce the performance of the architecture. A theoretical game-based methodology is proposed to improvise the performance and communication by routing the request packets in the NoC of the many core architectures and the throughput is maximized with reduced latency by using the stag-hunt game (SHG) model. The proposed communication algorithm routes the packets in an adaptive way by detecting the congestion in routers. The SHG based odd-even routing algorithm is adaptive and can divert the packets towards less congested routers using the information gathered about congestion in the system, so that the overall performance of the system in terms of latency and throughput is improved.

Cut and Forward: Safe and Secure Communication for FPGA System on Chips

Modern FPGA system on chips uses complex multimanager, multisubordinate on-chip communication networks. Processor cores, hardware accelerators, DMA engines, and other manager components actively access subordinate components like off-chip DRAM, on-chip memories, caches, and I/Os. On-chip communication networks are designed for high bandwidth and low latency. They use simple, fast transactions that largely assumes the managers cooperate. For example, it does not describe default mechanisms to ensure the safe behaviors of the managers using the on-chip interconnect. This lack of specification can lead to unpredictable behaviors: a single misbehaving, misconfigured, or malicious component can cause denial of service of shared resources. Clearly, this issue is critical in systems with safety and security constraints. Cut and forward is a novel switching method for multicomponent communication architectures on FPGA systems on chips (SoCs). Cut and forward leverages the programmability of FPGA SoCs to enable safe and secure bus access and is carefully designed to minimize its impact on performance and resource usage. Experiments show that Cut and forward ensures safety and security in realistic applications deployed on a commercial FPGA SoC from Xilinx including a popular deep neural network accelerator.

A 30% Efficient High-Output Voltage Fully Integrated Self-Biased Gate RF Rectifier Topology for Neural Implants

This paper presents a fully integrated RF energy harvester (EH) with 30% end-to-end power harvesting efficiency (PHE) and supports high output voltage operation, up to 9.3V, with a 1.07 GHz input and under the electrode model for neural applications. The EH is composed of a novel 10-stage self-biased gate (SBG) rectifier with an on-chip matching network. The SBG topology elevates the gate-bias of transistors in a non-linear manner to enable higher conductivity. The design also achieves >20% PHE range of 12-dB. The design was fabricated in 65 nm CMOS technology and occupies an area of 0.0732-mm2 with on-chip matching network. In addition to standalone EH characterization measurement results, animal tissue stimulation test was performed to evaluate its performance in a realistic neural implant application.

On Transferring Application Mapping Knowledge Between Differing MPSoC Architectures

The mapping of soft real-time applications onto a heterogeneous MPSoC target architecture is of high importance for meeting deadlines and minimizing secondary objectives like the consumed energy on the platform. In particular, for applications with input-dependent workload variation, hybrid application mapping (HAM) has crystallized itself as the state-of-the-art mapping approach that combines time-intensive design space exploration with lightweight run-time management. However, one general problem of HAM is that the explored mappings and models are highly specific to a certain target architecture. If the architecture is modified or changed (e.g., due to hardware upgrades, downgrades, or architectural degradation), the design-time optimization has to be repeated once again, which might take up to multiple weeks. As a remedy, this article proposes a twofold mapping transfer methodology that speeds up the design-time optimization for a novel or modified target architecture based on the knowledge we gained from the optimization for the original source architecture. First, we describe a greedy mapping transfer heuristic that provides feasible mappings for the new architecture in negligible optimization time. Second, we present a mapping refinement heuristic that improves these mappings even further while needing only a fraction of the optimization time of state-of-the-art approaches. As we show in the evaluation section, our approach can drastically speed up the convergence of the optimization for the novel architecture even if the sizes of the original and novel target architecture or the characteristics of the used resources differ significantly. Note that our approach assumes that the source and target architectures are both tile-based Network-on-Chip (NoC) meshes.

Secured Data Transmission Over Insecure Networks-on-Chip by Modulating Inter-Packet Delays

As the network-on-chip (NoC) integrated into an SoC design can come from an untrusted third party, there is a growing risk that data integrity and security get compromised when supposedly sensitive data flows through such an untrusted NoC. We thus introduce a new method that can ensure secure and secret data transmission over such an untrusted NoC. Essentially, the proposed scheme relies on encoding binary data as delays between packets travelling across the source and destination pair. The maximum data transmission rate of this inter-packet-delay (IPD)-based communication channel can be determined from the analytical model developed in this article. To further improve the undetectability and robustness of the proposed data transmission scheme, a new block coding method and communication protocol are also proposed. Experimental results show that the proposed IPD-based method can achieve a packet error rate (PER) of as low as 0.3% and an effective throughput of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {2.3\times 10^{5}}$ </tex-math></inline-formula> b/s, outperforming the methods of thermal covert channel, cache covert channel, and circuit-based encryption and, thus, is suitable for secure data transmission in unsecure systems.

RETRACTED: Optimized shortest path algorithm for on-chip board processor in large scale networks

In this paper, we present TriBA (Triplet based) NoC (network on-chip) architecture with 40 nodes referred as TriBA-NoC. TriBA-NoC is implemented in a multi-core 40 tile DDR-3 hardware. The nodes in the TriBA-NoC are connected through recursive triplets. We carried out the performance analysis in network simulator (NS-3) using several perspectives. We adopted TR-132 shortest routing path algorithm with novel router architecture for TriBA-NoC systems. The results of average packet latency for various patterns of traffic of a 40-core TriBA-NoC model are demonstrated. The results of the proposed 40-core TriBA-NoC model achieved better performances while compared to the TriBA.

Performance evaluation of modified mesh-based NoC architecture

With the advancement of technology in the field of VLSI, it is possible to integrate several computing elements onto a single chip. The performance of these single bus-based models still suffers from scalability on large-scale platforms. Therefore, network-on-chip (NoC) architecture integrating multiple cores in a single chip has emerged as an alternative. An efficient mapping is one of the most essential activities in high-performance multi-processor architectures. This research paper proposes an efficient core mapping and modified 2-D mesh NoC architecture. Every core is connected to the two routers via a network interface. In an efficient core mapping algorithm, the mapping region is selected based on Core Efficient Region (CER), which can improve the processor performance. The proposed core mapping algorithm is applied to the multimedia benchmarks. The experimental results show that the efficient core mapping algorithm outperforms the communication energy and performance when compared with other recent mapping algorithms.

Comparing timed-division multiplexing and best-effort networks-on-chip

Best-effort (BE) networks-on-chips (NOCs) are usually preferred over time-division multiplexed (TDM) NOCs in multi-core platforms because they are work-conserving and have lower (zero-load) latency. On the other hand, BE NOCs are significantly more expensive to implement than TDM NOCs because of their virtual channel buffers, allocators/arbiters, and (credit-based) flow control; functionality that a TDM NOC avoids altogether.The objective of this paper is to compare the performance of BE and TDM NOCs, taking hardware cost into consideration. The networks are compared using graphs showing average latency as a function of offered load. For the BE NOCs, we use the BookSim simulator, and for the TDM NOCs, we derive a queuing theory model and an associated TDM NOC simulator.Through experiments with both router architectures, packet length, link width, and different traffic patterns, we show that for the same hardware cost, a TDM NOC can provide higher bandwidth and comparable latency. We also show that the packet length is the most important factor affecting the TDM period, which again is the primary factor affecting latency. The best TDM NOC design for BE traffic uses single flit packets, wide links/flits, and a router with two pipeline stages: link and router traversal.

A transparent virtual channel power gating method for on-chip network routers

Since static power gradually dominates on-chip network power, power gating has been widely studied as a way to mitigate this trend. Even though many power gating methods reduce static power, they introduce new problems such as higher latency and hardware overhead, network disconnections, and low scalability. A new power gating method is therefore needed that can effectively reduce static power without sacrificing the benefits of the on-chip network. In this paper, we propose an efficient power gating method for virtual channels. Firstly, neighboring routers no longer exchange and store each other’s power states with handshake signals, and each router independently decides when to sleep or wake up based on traffic loads. Secondly, in order to eliminate flit stalls and reduce network latency, we propose a modified credit-based flow control and provide a detailed hardware implementation. Finally, bypasses allow packets to reach processing elements (PEs) or downstream routers without waking up sleeping virtual channels, which reduces breakeven time (BET) violations and cumulative wake-up latency while ensuring network connectivity. Based on the evaluation, under real applications, the proposed power gating method reduces static energy by an average of 82.5% compared to the baseline, while increasing latency overhead by 13.7% and area overhead by 6.48%.

Enabling circuit-switching in modern on-chip networks

Contemporary flow control mechanisms, especially virtual channels, are employed by modern on-chip networks to allow better utilization of the link bandwidth through buffering and packet switching. Despite of being the de facto option in designs, they are also the sources of large energy footprint and long per-hop latency. On the other hand, dated and simpler flow controls such as circuit switching can draw far less power while offering an end-to-end latency analogous to wire delay. In this paper, we therefore take a further step from utilizing a single flow control mechanism within the network to allowing circuit-switching to work alongside virtual channels, which provides latency-competitive and energy-efficient on-chip network designs. Furthermore, to enable circuit switching in modern networks-on-chip, we present two independent proposals so that circuits can be formed in a network either temporally or spatially. In our evaluations, we find that both of our proposals can help achieve a very competitive latency per flit, for up to 30% lower with the temporal approach and for up to 10% lower with the spatial approach, while also dramatically suppressing the energy footprint with either approach by up to 27% and 25%, respectively.

A Novel Hybrid Hexagonal Star Topology for On-Chip Interconnection Networks

Network-on-Chip (NoC) is an emerging and efficient on-chip interconnection network. NoC is expected to be the communication backbone of next-generation Multi-processor System-on-Chip (MPSoC) architectures. Topology is a crucial design aspect of NoC, as it affects the performance of the interconnection network. This paper proposes a novel, scalable, hybrid Hexagonal Star (HS) topology for on-chip interconnection networks. Properties of the proposed topology have been explored and compared with those of Mesh, Torus and Honeycomb Mesh topologies. The performance of the Hexagonal Star topology has been evaluated and compared with that of Mesh topology for different scenarios. The comparative studies of topological properties have indicated that the proposed topology can be a potential choice for on-chip interconnection networks. The simulation results have shown that the proposed topology outperforms Mesh topology in terms of latency for low traffic loads. For different traffic patterns and traffic loads, HS topology has registered a reduction of packet latency ranging from 15% to 50% and from 9% to 23% for 18 nodes and 32 nodes, respectively, compared to Mesh topology.

Anticipative QoS Control: A Self-Reconfigurable On-Chip Communication.

A self-reconfigurable Network-on-Chip (NoC) architecture that supports anticipative Quality of Service (QoS) control with penetrative switch ability is proposed to enhance the performance of bidirectional-channel NoC communication while supporting prioritized packet transmission services. The anticipative QoS control not only allows each communication channel to be dynamically self-configured to transmit flits in either direction for a better channel utilization of on-chip hardware resources, but also enhances the latency performance for QoS services. The proposed anticipative control is based on penetratingly observing channel direction requests of routers that is two hops away from the current one. The added ability enables a router to allocate high-priority packets to a dedicated virtual channel and then rapidly bypass it to the next destination router. The provided flexibility of packet switch promises better channel bandwidth utilization, lower packet delivery latency, and furthermore guarantees the high-priority packets being served with a better QoS. Accordingly, in this paper, an enhanced NoC architecture supporting the hybrid anticipative QoS, penetrative switch, and bidirectional-channel control, namely Anticipative QoS Bidirectional-channel NoC (AQ-BiNoC) is presented. Tested with cycle-accurate synthetic traffic patterns, significant performance enhancement has been observed when the proposed AQ-BiNoC architecture is compared against conventional NoC designs.

ASCENT: Communication Scheduling for SDF on Bufferless Software-Defined NoC

Bufferless software-defined network-on-chip (NoC) is a promising alternative to conventional dynamic routing as it offers predictable data movement with real-time guarantees. Existing time-division multiplexing (TDM)-based mechanisms for predictability assume the worst-case communication pattern (e.g., all-to-all) and compute a fixed schedule wherein the cores can only communicate during the allocated time slots. These approaches lead to low application throughput as they cannot adapt to application characteristics. In this article, we present an application specific, non-TDM-based communication scheduling mechanism for bufferless software-defined NoCs. We choose the synchronous dataflow (SDF) model of computation to represent the input streaming applications. We propose ASCENT, a novel offline approach that takes the SDF-specified streaming application and the NoC architecture as input, exploits the task interactions and the timing information in the SDF, and generates the task-to-core mapping and communication schedule that is represented compactly in hardware. ASCENT achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.8\times $ </tex-math></inline-formula> better performance on average than existing TDM-based NoCs and manages to achieve the performance of an ideal dynamically routed NoC, yet ensuring predictability.

Optimal Mapping of Spiking Neural Network to Neuromorphic Hardware for Edge-AI.

Neuromorphic hardware, the new generation of non-von Neumann computing system, implements spiking neurons and synapses to spiking neural network (SNN)-based applications. The energy-efficient property makes the neuromorphic hardware suitable for power-constrained environments where sensors and edge nodes of the internet of things (IoT) work. The mapping of SNNs onto neuromorphic hardware is challenging because a non-optimized mapping may result in a high network-on-chip (NoC) latency and energy consumption. In this paper, we propose NeuMap, a simple and fast toolchain, to map SNNs onto the multicore neuromorphic hardware. NeuMap first obtains the communication patterns of an SNN by calculation that simplifies the mapping process. Then, NeuMap exploits localized connections, divides the adjacent layers into a sub-network, and partitions each sub-network into multiple clusters while meeting the hardware resource constraints. Finally, we employ a meta-heuristics algorithm to search for the best cluster-to-core mapping scheme in the reduced searching space. We conduct experiments using six realistic SNN-based applications to evaluate NeuMap and two prior works (SpiNeMap and SNEAP). The experimental results show that, compared to SpiNeMap and SNEAP, NeuMap reduces the average energy consumption by 84% and 17% and has 55% and 12% lower spike latency, respectively.

Realization of optical logic gates using on-chip diffractive optical neural networks

Optical computing is highly desired as a potential strategy for circumventing the performance limitations of semiconductor-based electronic devices and circuits. Optical logic gates are considered as fundamental building blocks for optical computation and they enable logic functions to be performed extremely quickly without the generation of heat and crosstalk. Here, we discuss the design of a multi-functional optical logic gate based on an on-chip diffractive optical neural network that can perform AND, NOT and OR logic operations at the wavelength of 1.55 µm. The wavelength-independent operation of the multi-functional logic gate at seven wavelengths (over a bandwidth of 60 nm) is also studied which paves the way for wavelength division multiplexed parallel computation. This simple, highly-integrable, low-loss, energy-efficient and broadband optical logic gate provides a path for the development of high-speed on-chip nanophotonic processors for future optical computing applications.

SMA: A constructive partitioning based mapping approach for Networks-on-Chip

This paper proposes a constructive partitioning approach as an effective mapping approach for 2D Networks-on-Chip. Cluster-based mapping approach offers a promising improvement on the fastest initial mapping against the standard Networks-on-Chip (NoC) architecture. In this paper, the spectral partitioning algorithm is adopted for the fastest mapping with NoC, named SMA. The proposed spectral partitioning-based mapping approach (SMA) explores the efficacious NoC mapping concerning communication bandwidth, average hop counts, and total power consumption NoC architecture. The experimental analysis indicates that the proposed SMA outperforms existing partitioning approaches.

Impedance modeling and analysis of multi-stacked on-chip power distribution network in 3D ICs

An accurate impedance modeling of a multi-stacked on-chip power distributed network (PDN) based on through-silicon-vias (TSVs) is vitally important to estimate the electrical performance in three-dimensional integrated circuits (3D ICs). This paper proposes a method for calculating the impedance matrix of the multi-stacked on-chip PDN, which mainly consists of arbitrarily distributed TSVs and grid-type on-chip PDNs. First, a real stack-up structure of a multi-stacked on-chip PDN is separated into discrete components intentionally. Then, the equivalent lumped circuit models of all discrete components are assembled into a whole to build the transmission matrix of the multi-stacked on-chip PDN through the relationship between the nodal voltage and the nodal current. Finally, the impedance matrix can be derived through the transmission matrix. In this paper, the coupling of the arbitrarily distributed TSVs and the distributional effect of the on-chip PDN are considered in the impedance matrix through the transmission matrix method (TMM). The proposed method replaces the simulation of the complex equivalent circuit model with the matrix calculation. The verification results show that the deviation of resonant frequency is about 6 $$\%$$ and the conversation of the simulation time is about 99.9 $$\%$$ compared with the HFSS model. It can accurately and quickly calculate the impedance of the multi-stacked on-chip PDN.