Improving power and performance of on-chip network through virtual channel sharing and power gating

Abstract

Networks-on-Chip (NoCs) are becoming the communication backbone in multicore chips. The router buffer holds a critical significance for the communication performance of NoC. However, the bursty traffic means that the buffers are idle for many periods and generate a significant amount of static power. Moreover, due to the uneven traffic distribution, some buffers within the router stand idle even at network saturation. Both the performance and power budget of NoC heavily depends on the router’s buffer budget. Therefore, we desperately demand a mechanism to maximize the usage of idle buffers to balance the load and improve the performance ceiling of NoC. Dynamically based on network traffic, early switching on or off of buffers to save power consumption. We propose a modified microarchitecture of the virtual channel sharing router, MVCR. The MVCR innovatively applies aggressive fine-grained power gating mechanisms to the idle buffers of each directional input port (east, west, south, and north) to achieve static power savings. Moreover, the MVCR further extends the sleeping VC period through an efficient packet-transmission adjustment mechanism, thus achieving maximum static power savings and improved network performance. Synthetic applications and real benchmarks have been used to validate MCVR. Compared to traditional router scheme, MVCR increases throughput by 30%, reduces power consumption by 47%, and has a latency overhead of about 6%. The key performance metrics are better than other solutions, and the added area cost is moderate.