Efficient application mapping approach based on grey wolf optimization for network on chip

Abstract

In modern chip designs with multiple processors, network-on-chip (NoC) has emerged as a critical solution, offering scalability, flexibility, modularity, and efficiency. However, a significant challenge in application mapping is minimizing communication costs as they directly affect performance and energy consumption. Although several mapping algorithms have been developed, they often suffer from complexity, suboptimal performance, and slow convergence. To address these challenges, this paper proposes a novel approach for mapping using the grey wolf optimization (GWO) technique inspired by nature. The proposed GWO-based mapping approach for NoC (GNoC) is augmented with an effective clustering-based initial mapping strategy, further enhancing its capabilities. Furthermore, a second heuristic algorithm is introduced, incorporating a modified GWO method with polynomial regression (GNoC-PR). This modification optimizes the runtime efficiency and enhances the overall mapping quality. The proposed method was evaluated through comprehensive simulations and compared with state-of-the-art solutions. The results demonstrate that the proposed algorithm outperforms existing methods in several key metrics, including a power consumption reduction of 19.7%, energy efficiency improvement of 17%, and a significant 40% decrease in computational overhead on average. To validate the effectiveness of our mapping technique, we evaluated both embedded and synthetic applications, considering various metrics such as communication cost, average network latency, and power consumption.