Negative Capacitance Transistor Research Articles

Anomalously Beneficial Gate-Length Scaling Trend of Negative Capacitance Transistors

The Negative Capacitance Field Effect Transistors exhibit excellent SS and DIBL improvements from the control MOSFET devices at very short gate lengths, a phenomenon which cannot be explained using conventional MOSFET theory. This benefit arises from an effect which acts similarly to decreasing the equivalent-oxide thickness at short gate lengths. The effect is observed in both TCAD simulations and experiments, and is explained by the conjunction of the source/drain inner fringing field and the nonlinear polarizability of ferroelectric materials. The results present a sharp contrast to conventional scaling theory and bode well for extending the MOSFET gate length scaling limit.

Band alignments at Hf1-Zr O2/Si and Hf0.52Zr0.48O2/Si0.55Ge0.45 interfaces

Abstract Hf1-xZrxO2 films have attracted significant attention for applications in ferroelectric memory and negative capacitance transistors due to their ferroelectric properties and high compatibility to CMOS integration. X-ray photoelectron spectroscopy (XPS) was utilized to characterize the energy band alignments of Hf1-xZrxO2/Si and bandgaps of Hf1-xZrxO2 with different Zr compositions. Results show with the increment of Zr composition in Hf1-xZrxO2 from 0 to 1, the valence band offset ΔEv for Hf1-xZrxO2/Si interfaces increases from 2.09 to 2.94 eV, while the conduction band offset ΔEc decreases from 2.37 to 1.06 eV. This is resulted from the increasing Zr composition leading to a decrement of bandgap and electron affinity in Hf1-xZrxO2. Both ΔEv and ΔEc are all above 1 eV, which is large enough to block electrons and holes for carrier transport in channel regions for the Hf1-xZrxO2 based transistors. The band alignment for Hf0.52Zr0.48O2/Si0.55Ge0.45 was also investigated exhibiting a much larger ΔEv and a slightly lower ΔEc as compared to Hf0.52Zr0.48O2/Si.

Proposal for Capacitance Matching in Negative Capacitance Field-Effect Transistors

Negative-capacitance transistors use ferroelectric (FE) material in the gate-stack to improve the transistor performance. The extent of the improvement depends on the capacitance matching between the FE capacitance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\textsf {fe}}$ </tex-math></inline-formula> ) and the underlying MOS transistor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\textsf {MOS}}$ </tex-math></inline-formula> ). Since both <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\textsf {MOS}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\textsf {fe}}$ </tex-math></inline-formula> have strong non-linearity, it is difficult to achieve a good matching for the entire operating gate voltage range. In this letter, we discuss a new approach using multi-layer FE to engineer the shape of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\textsf {fe}}$ </tex-math></inline-formula> . The proposed method is validated using the TCAD simulation of negative-capacitance FDSOI transistor, and the results show that it leads to better sub-threshold swing as well as lower power supply <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\textsf {dd}}$ </tex-math></inline-formula> compared with a prototype single-layer negative-capacitance field-effect transistor.

Negative Capacitance Black Phosphorus Transistors With Low SS

Negative capacitance (NC) shows great potential to enable transistors with the steeper slope, which is very useful for voltage/power applications. Black phosphorus (BP) is theoretically predicted as good channel materials for NC-FETs. However, the experimental demonstration of BP has so far remained elusive. Here, for the first time, NC transistors based on BP have been demonstrated. By connecting to a 20-nm HfZrO ferroelectric capacitor, both two types of BP transistors show lower subthreshold slope (SS). For 5-nm AlOx BP transistor, the SS decreases from 200 to 104 mV/dec. The experimental results are analyzed with the BP-NCFET model, and the calculated transfer curve can fit well with the experimental curve, which proves the validation of the model. Our work sheds light on using NC BP FETs for low-power flexible electronics applications.

Implementation of Dopant-Free Hafnium Oxide Negative Capacitance Field-Effect Transistor

For the first time, we successfully demonstrated the dopant-free HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> negative capacitance (NC) transistor featuring a low gate-overdrive voltage and a nearly hysteresis-free sub-40 mV/dec swing. These excellent performances can be ascribed to the reduction of the monoclinic phase suppressed with the thickness scaling and gate stress engineering favorably rearranging oxygen vacancies to boost orthorhombic phase transition. The highly scalable and dopant-free NC transistor shows the potential for the application of advanced CMOS technology.

Negative Capacitance Transistors

In recent years, the negative capacitance effect in ferroelectric (FE) materials has attracted significant attention from many researchers around the world. The negative capacitance effect promises to reduce the voltage requirement in conventional complementary metal–oxide–semiconductor transistors below what is otherwise believed to be the Boltzmann limit. In this paper, our objective is to discuss the fundamental underpinning of the negative capacitance effect and describe how it can be utilized for transistors. We shall start with a thermodynamic perspective to understand where the reduction in energy dissipation comes from. We then proceed to derive the S curve in an FE material from fundamental principles. The central result of this paper is to associate the negative slope region in the S curve to a physically definable configuration of dipoles in the crystal structure. The design of a negative capacitance transistor is essentially an exercise of stabilizing the FE in the negative slope region of the S curve using the semiconductor capacitance as a series capacitor.

Numerical Investigation of Short-Channel Effects in Negative Capacitance MFIS and MFMIS Transistors: Subthreshold Behavior

In this paper, we analyze the impact of length scaling on the ON-state operation of the two classes of double-gate negative capacitance transistors: metal–ferroelectric–metal–insulator–semiconductor (MFMIS) and metal–ferroelectric–insulator–semiconductor (MFIS). We show that for long-channel structures, MFMIS configuration shows a higher ON current than the MFIS due to a lower drain saturation voltage of the latter. For short-channel cases, we compare these negative capacitance field effect transistors (NCFETs) under two scenarios: equal flat band voltages (iso- ${V}_{\textsf {FB}}$ ) and equal OFF currents (iso- ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ). In iso- ${V}_{\textsf {FB}}$ condition, a higher negative differential conductance (NDC) effect in the MFMIS suppresses its ON current below that of the MFIS. However, the MFMIS provides a higher ON current than the MFIS for all the channel lengths under iso- ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ condition. We further investigate the influence of quantum mechanical effects and velocity saturation of carriers on the electrical characteristics of short-channel NCFETs. We also explore the impact of inner and outer spacer fringings in NCFETs. We find that the ferroelectric voltage gain in NCFETs with spacers increases with the channel length scaling, which provides a further improvement in the ON current contrary to those without spacers. Moreover, increase in the spacer permittivity also boosts both the ON current and the NDC.

Gate Stack Engineering in 2D Semiconductor FETs for Electronic Applications

Two-dimensional (2D) transition metal dichalcogenides (TMDs), such as MoS2 and WS2 have been extensively studied in various electronic fields [1,2] due to their unique physical and electronic properties, maintaining excellent semiconductor characteristics even at one atomic layer thickness. Field-effect transistors (FETs) bases on these novel 2D materials have been largely considered as the building blocks in future nanoelectronic device and circuit technologies. Since the first report on the electrical performance of MoS2 transistor in 2011 [3], massive efforts have been made in seeking for high-quality materials and advanced device structure. So far, the lack of mature synthesis approaches to grow high-crystalline, defect-free, large-area and reproducible TMD films has left prevalence to the fabrication by mechanical exfoliation which has been widely used in the research on graphene. The “scotch-tape” method is advantageous in obtaining high-quality single-crystal 2D samples with least defects, and the flake thickness can be ranged from monolayer to quite thick providing excellent subjects for the study on both physical properties and device applications. Generally, the exfoliated TMD samples were taped onto a Si substrate covered with a thick SiO2 (250~300 nm) or high-k dielectric film for easier optical observation to locate and identify the layer number of the ultra-thin TMD flakes using a microscope. However, thick gate dielectric will lead to poor gate control and much higher gate voltage is required to induce substantial source-drain current. An alternative method is to transfer the exfoliated sample on SiO2/Si surface to other desired substrates. But the 2D flakes can easily get damaged and contaminated during such transfer process leading to degraded interface quality and device behavior. Perhaps the most common approach to enhance gate control is to use top-gate structure with typical high-k/metal gate combination. However, due to the absence of dangling bonds or functional groups on the MoS2 basal planes, the initial growth of high-k dielectric by atomic layer deposition on MoS2 surface is determined by physical adsorption of the precursors [4]. It can easily lead to discontinuous coverage and serious gate leakage. This is the major reason for the relatively thick top gate dielectric in most reported work. Furthermore, the fact that only dielectric deposition at low temperature (e.g. below 200 oC by Liu et al. [5]) can avoid the island-like morphology will inevitably hamper the electrical properties of the gate dielectric by impurities or defects like pinholes. While there is still some controversy regarding the surface pretreatment prior to the top-gate dielectric deposition, it is generally understood that back-gate FET architecture can best preserve the intrinsic properties of these 2D materials without any surface oxidation or lattice damage. In this work, we carefully engineered the back-gate stack in MoS2 FETs to enhance the gate control as well as to achieve similar optical contrast to that on ~300 nm SiO2/Si for optical identification of 2D flakes. As shown in Fig. 1, the optimized Al2O3/ITO/SiO2 stack with the transparent ITO working as the back-gate electrode significantly enhanced the gate control as well as light sensing capabilities. We also studied the 1/f noise characteristics and the application of the stack engineering in MoS2 non-volatile memory and steep-slope negative capacitance transistors (Fig. 2 and 3). This work shows that our engineered stack is an attractive platform to study the physical properties and electronic device applications of the novel 2D materials.

(Invited) Ferroelectric Oxides and Negative Capacitance for Ultra-low Power Computing

Thanks to the sub-60 mV/decade switching characteristics, negative capacitance transistors based on ferroelectric gate oxides can enable the reduction of power supply voltage and the power dissipation in future nodes. This talk will give an overview of the exciting developments in the field of negative capacitance over the past nine years starting from the theoretical prediction in 2008 to the clean experimental demonstration of this phenomenon in ferroelectric materials and transistors recently. All three aspects of this technology: physics, materials and devices will be discussed.

Negative Capacitance beyond Ferroelectric Switches.

Negative capacitance transistors are a unique class of switches capable of operation beyond the Boltzmann limit to realize subthermionic switching. To date, the negative capacitance effect has been predominantly attributed to devices employing an unstable insulator with ferroelectric properties, exhibiting a two-well energy landscape, in accordance with the Landau theory. The theory and operation of a solid electrolyte field effect transistor (SE-FET) of subthreshold swing less than 60 mV/dec in the absence of a ferroelectric gate dielectric are demonstrated in this work. Unlike ferroelectric FETs that rely on a sudden switching of dipoles to achieve negative capacitance, we demonstrate a distinctive mechanism that relies on the accumulation and dispersion of ions at the interfaces of the oxide, leading to a subthreshold slope (SS) as low as 26 mV/dec in these samples. The frequency of operation of these unscaled devices lies in a few millihertz because at higher or lower frequencies, the ions in the insulator are either too fast or too slow to produce voltage amplification. This is unlike Landau switches, where the SS remains below 60 mV/dec even under quasi-static sweep of the gate bias. The proposed FETs show a higher on-current with a thicker oxide in the entire range of gate voltage, clearly distinguishing their scaling laws from those of ferroelectric FETs. Our theory, validated with experiment, demonstrates a new class of devices capable of negative capacitance that opens up alternate methods of steep switching beyond the traditional approach of ferroelectric or memristive FETs.

Compact Modeling of Drain Current, Charges, and Capacitances in Long-Channel Gate-All-Around Negative Capacitance MFIS Transistor

In this paper, we present a surface potential-based explicit continuous model for a metal-ferroelectric-insulator-semiconductor (MFIS) type gate-all-around negative capacitance transistor (GAA-NCFET). Unlike previously reported models, an explicit formulation to calculate the electrical characteristics of GAA-NCFET is proposed. Our model includes the radial dependence of the electric field in the ferroelectric, ignored in the previous works and accurately captures ferroelectric material parameter variations in the nonhysteretic regime. In contrast to bulk NCFETs, GAA-NCFET characteristics show different bias dependence due to the absence of bulk charge. We also present analytical expressions for the terminal charges which are essential to obtain the trans-capacitances for transient simulations. We find that, compared with conventional MOSFETs, the gate charge saturates to a different fraction of its maximum value. Furthermore, the modeling of quantum mechanical effect and overlap capacitances in an MFIS NCFET structure is discussed. Finally, the proposed model has been implemented in Verilog-A and tested for the transient response of ring oscillator in a commercial circuit simulator.

(Invited) Negative Capacitance Transistors

Negative capacitance is a new state within ferroelectric materials that exploits a region of thermodynamic space that is otherwise forbidden. In the conventional thinking, a material that goes through a ferroelectric phase transition, develops an energy landscape such that two degenerate states are separated by an energy barrier. This gives the energy landscape the shape of a ‘W’. By itself, the ferroelectric sits in one of the degenerate states where its energy is minimized. Given that these states correspond to the minima of the energy function, G, the curvature, i.e., the permittivity is positive. Note also, that because of the ‘W’ landscape, these energy minima occur at non-zero polarization values, meaning a ferroelectric material has non-zero charge in its equilibrium state. However, this very well-known and well understood situation changes when a dielectric is brought in series connection with the ferroelectric. The parabolic energy landscape of the dielectric, when added to the ‘W’ landscape of the ferroelectric, can lead to a situation where the overall energy landscape of the composite system looks parabolic. This means that the energy minimum of the composite system now occurs at P~0, where, locally, the ferroelectric has an energy minima. Thus, the competing forces of electrostatics can lead to a situation, remarkably, where a ferroelectric can be stabilized in equilibrium at a state where its own energy landscape has a maximum, i.e., a negative curvature , and therefore a negative permittivity. The negative permittivity state thus stabilized has important implications for transistors. A transistor looking from the gate essentially acts as a series combination of two capacitors: the gate oxide capacitor and the channel capacitor. When the gate oxide is replaced by an appropriate ferroelectric, this series combination looks exactly like the ferroelectric dielectric combination discussed in the previous paragraph and can stabilize the ferroelectric material at a state of negative capacitance. At this state, the total capacitance of the series combination is enhanced, leading to more charge at the channel at the same voltage. This boost of charge, in turn, leads to larger current at the same voltage. In fact, this boost makes it possible to reduce supply voltage of transistors below the traditional Boltzmann limit --- often termed as the Boltzmann tyranny. In this talk, we shall briefly discuss the thermodynamic underpinnings that make it possible to go beyond the Boltzmann limit. The recent advent of HfO2 based ferroelectric materials has enabled integration of thin ferroelectric gate dielectrics with high performance transistors. Exploiting this capability, many groups around the world, both in academia and in the industry, have demonstrated the fundamental effect and the Negative Capacitance Transistors. We shall describe our current understanding of the recent experimental work and also discuss some of the salient features by which negative capacitance transistors are very different from conventional transistors. We will emphasize the fact that negative capacitance effect should not be viewed either as a new high-K material problem or a booster technology such as strain. Rather, it is necessary to realize that negative capacitance transistor is, in fact, a completely new device, that operates on a new physical principle, and to extract the most benefit from this technology, it is important to go back to device design from the scratch, rather simply following the classical scaling rules. I shall discuss some of our recent results that promise to significantly improve the energy efficiency of the latest technology node and also provide a viable pathway to extend scaling beyond what is currently believed to be the end of the roadmap.

Nonideality of Negative Capacitance Ge Field-Effect Transistors Without Internal Metal Gate

We demonstrate negative capacitance (NC) Ge field-effect transistors (FETs) utilizing the TaN/HfZrO x /SiO2 gate stack. Typical characteristics of NC transistors, including the sub-60 mV/decade subthreshold swing (SS), the gate capacitance ${C} _{G}$ peak, and the negative differential resistance effect are achieved in NC Ge FETs without internal metal gate. Significant ${C} _{\textit {G}}$ peak, as the evidence of NC effect is obtained in NC transistors at the frequency up to MHz. Ferroelectric Ge FETs with counterclockwise ${I} _{\text {DS}} - {V} _{\text {GS}}$ loops due to trapping/detrapping, opposite hysteresis to the NC switching are also observed. The NC transistor has much steeper SS compared to the device dominated by the trapping/detrapping process. Statistical results show that only 10% of devices are dominated by the NC effect, and the density of defects in ferroelectric needs to be reduced to improve the yield of NC transistors.

Negative Differential Resistance in Negative Capacitance FETs

We report the investigation of negative differential resistance (NDR) in negative capacitance (NC) germanium (Ge) pFETs. The NDR in NC transistors is attributed to the coupling of drain voltage to the internal gate voltage ${V}_{\text {int}}$ via the gate-to-drain capacitance. It is demonstrated that NDR strongly depends on the matching between the NC induced by ferroelectric capacitance ${C}_{\text {FE}}$ and the positive capacitance associated with the underlying transistor capacitance ${C}_{\text {MOS}}$ . For the non-hysteretic devices, NDR gets pronounced with an increased thickness of ferroelectric film ${t}_{\text {fe}}$ and ${V}_{\text {GS}}$ . This is attributed to the fact that the drain coupling factor is improved with an increased ${t}_{\text {fe}}$ and ${V}_{\text {GS}}$ , leading to the better matching between ${C}_{\text {FE}}$ and ${C}_{\text {MOS}}$ . For the hysteretic NC transistors, however, NDR is only obtained at the lower ${V}_{\text {GS}}$ , but not observed at higher ${V}_{\text {GS}}$ .

Effects of the Variation of ${V}_{\text {GS}}$ Sweep Range on the Performance of Negative Capacitance FETs

We report the first investigation of the impacts of gate voltage sweep range ${V}_{\text {GS,range}}$ on the performance of negative capacitance (NC) transistors. As ${V}_{\text {GS,range}}$ is reduced, NC GeSn pFETs generally exhibit an increased hysteresis or a transition from non-hysteretic to hysteretic, and show a degradation of ${I}_{\text {DS}}$ . This is due to the reduction of the ratio of remnant polarization ${P}_{\text {r}}$ to coercive field ${E}_{\text {c}}$ with the reduced voltage across the HZO. Interestingly, however, some NC devices show a negligible impact of ${V}_{\text {GS,range}}$ on hysteresis and ${I}_{\text {DS}}$ . The NC transistor demonstrates a stable hysteresis in 139–149 mV range and the improved SS and ${I}_{\text {DS}}$ over the control device, with a reduced ${V}_{\text {GS,range}}$ of 0.5 to −0.5 V. To obtain device performance independent of ${V}_{\text {GS,range}}$ , the ratio of ${P}_{\text {r}}/{E}_{\text {c}}$ of the HZO needs to stabilize in a very small ${V}_{\text {GS,range}}$ .

A Graphene‐Based Filament Transistor with Sub‐10 mVdec−1 Subthreshold Swing

AbstractThere is a growing trend of developing steep slope transistors with subthreshold swing (SS) below 60 mV dec−1. At present, there are mainly three kinds of steep slope transistors: tunneling transistor, negative capacitance transistor, and nano‐electromechanical relay. Here, a new kind of steep slope transistor named “filament transistor” is proposed with SS down to sub‐10 mV dec−1. Due to the gate E‐filed can penetrate through the graphene, the gate can effectively control the filament formation/rupture inside the 5 nm AlOx with very steep slope. In reverse sweep, the gate can induce the filament formation with SS down to 4.6 mV dec−1. In forward sweep, the gate can break the filament with SS down to 12.2 mV dec−1. Taking the advantages of nanofilament, the filament transistor holds a great potential to scaling down to 5 nm without performance changing.

Ferroelectric HfZrOx-based MoS2 negative capacitance transistor with ITO capping layers for steep-slope device application

A negative capacitance field-effect transistor (NCFET) built with hafnium-based oxide is one of the most promising candidates for low power-density devices due to the extremely steep subthreshold swing (SS) and high on-state current induced by incorporating the ferroelectric material in the gate stack. Here, we demonstrated a two-dimensional (2D) back-gate NCFET with the integration of ferroelectric HfZrOx in the gate stack and few-layer MoS2 as the channel. Instead of using the conventional TiN capping metal to form ferroelectricity in HfZrOx, the NCFET was fabricated on a thickness-optimized Al2O3/indium tin oxide (ITO)/HfZrOx/ITO/SiO2/Si stack, in which the two ITO layers sandwiching the HfZrOx film acted as the control back gate and ferroelectric gate, respectively. The thickness of each layer in the stack was engineered for distinguishable optical identification of the exfoliated 2D flakes on the surface. The NCFET exhibited small off-state current and steep switching behavior with minimum SS as low as 47 mV/dec. Such a steep-slope transistor is compatible with the standard CMOS fabrication process and is very attractive for 2D logic and sensor applications and future energy-efficient nanoelectronic devices with scaling power supply.

Negative Capacitance Ge PFETs for Performance Improvement: Impact of Thickness of HfZrO&lt;italic&gt;x&lt;/italic&gt;

We report a comparative investigation of the negative capacitance (NC) Ge pFETs with different thicknesses of HfZrO x (HZO). Although the NC transistors with 6.6 nm HZO exhibit the sub-60 mV/decade subthreshold swing, the hysteresis inevitably occurs. The hysteresis-free characteristics are demonstrated in the NC Ge pFETs with 4.5 and 3.7 nm HZO. The influence of postannealing temperature on device performance is dependent on the thickness of HZO. With the postannealing at 450 °C, NC transistors with 4.5 and 3.7 nm HZO achieve 23% and 11% ${I}_{\textsf {DS}}$ improvement, respectively, over the control devices, at a ${V}_{\textsf {GS}}$ – ${V}_{\textsf {TH}}$ of −1.0 V and a ${V}_{\textsf {DS}}$ of –0.05 V. However, a higher postannealing temperature of 550 °C leads to the significant degradation in NC device with 4.5 nm HZO compared with the control device. It is further observed that, with the fixed HZO thickness and postannealing temperature, ${I}_{\textsf {DS}}$ of the NC Ge pFETs is improved as the ${C}_{G}$ peak gets increased.

Physical Insights on Negative Capacitance Transistors in Nonhysteresis and Hysteresis Regimes: MFMIS Versus MFIS Structures

We present a comprehensive comparison of the two different types of ferroelectric negative capacitance FET (NCFET) structures: metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal-ferroelectric-insulator-semiconductor (MFIS). A new segmentation approach is proposed to simulate MFIS NCFET, which correctly takes care of the nonuniformity in potential and horizontal electric field at the ferroelectric–oxide interface. We show that MFMIS NCFET provides a higher ON-current than MFIS NCFET except for the ferroelectrics with very low remnant polarization ( ${P}_{r}$ ) in the high operating voltage regime. We find that this behavior is caused by a reduction or enhancement of the longitudinal electric field in the channel of MFIS structure depending upon ${P}_{r}$ of the ferroelectric and the operating voltage. Moreover, there exists an optimum ${P}_{r}$ which provides maximum ON-current for both the devices. We also find that MFIS NCFET is more prone to hysteresis and starts showing a hysteretic behavior at a lower ferroelectric thickness compared with MFMIS NCFET.

Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance

Negative capacitance field-effect transistor (NCFET) addresses one of the key fundamental limits in technology scaling, akin to the non-scalable Boltzmann factor, by offering a sub-threshold swing below 60 mV/decade. In this paper, we investigate how the NCFET technology can open the doors not only for the continuation of Moore’s law, which is approaching its end, but also for reviving Dennard’s scaling, which stopped more than a decade ago. We study NCFET for the 7-nm FinFET technology node, from physics to processors and demonstrate that prior trends in processor design with respect to voltage and frequency can be revived with the NCFET technology. Our work focuses on answering the following three questions towards drawing the impact of NCFET technology on computing efficiency: In how far NCFET technology will enable processors: 1) to operate at higher frequencies without increasing voltage; 2) to operate at higher frequencies without increasing power density, which is substantial, because maintaining on-chip power densities under tight constraints due to limited cooling capabilities is inevitable; and 3) to operate at lower voltages, while still fulfilling performance requirements, which is substantial for the emerging Internet of Things, in which available power budgets for such devices are typically very restricted.