Gate Stack Engineering in 2D Semiconductor FETs for Electronic Applications

Abstract

Two-dimensional (2D) transition metal dichalcogenides (TMDs), such as MoS2 and WS2 have been extensively studied in various electronic fields [1,2] due to their unique physical and electronic properties, maintaining excellent semiconductor characteristics even at one atomic layer thickness. Field-effect transistors (FETs) bases on these novel 2D materials have been largely considered as the building blocks in future nanoelectronic device and circuit technologies. Since the first report on the electrical performance of MoS2 transistor in 2011 [3], massive efforts have been made in seeking for high-quality materials and advanced device structure. So far, the lack of mature synthesis approaches to grow high-crystalline, defect-free, large-area and reproducible TMD films has left prevalence to the fabrication by mechanical exfoliation which has been widely used in the research on graphene. The “scotch-tape” method is advantageous in obtaining high-quality single-crystal 2D samples with least defects, and the flake thickness can be ranged from monolayer to quite thick providing excellent subjects for the study on both physical properties and device applications. Generally, the exfoliated TMD samples were taped onto a Si substrate covered with a thick SiO2 (250~300 nm) or high-k dielectric film for easier optical observation to locate and identify the layer number of the ultra-thin TMD flakes using a microscope. However, thick gate dielectric will lead to poor gate control and much higher gate voltage is required to induce substantial source-drain current. An alternative method is to transfer the exfoliated sample on SiO2/Si surface to other desired substrates. But the 2D flakes can easily get damaged and contaminated during such transfer process leading to degraded interface quality and device behavior. Perhaps the most common approach to enhance gate control is to use top-gate structure with typical high-k/metal gate combination. However, due to the absence of dangling bonds or functional groups on the MoS2 basal planes, the initial growth of high-k dielectric by atomic layer deposition on MoS2 surface is determined by physical adsorption of the precursors [4]. It can easily lead to discontinuous coverage and serious gate leakage. This is the major reason for the relatively thick top gate dielectric in most reported work. Furthermore, the fact that only dielectric deposition at low temperature (e.g. below 200 oC by Liu et al. [5]) can avoid the island-like morphology will inevitably hamper the electrical properties of the gate dielectric by impurities or defects like pinholes. While there is still some controversy regarding the surface pretreatment prior to the top-gate dielectric deposition, it is generally understood that back-gate FET architecture can best preserve the intrinsic properties of these 2D materials without any surface oxidation or lattice damage. In this work, we carefully engineered the back-gate stack in MoS2 FETs to enhance the gate control as well as to achieve similar optical contrast to that on ~300 nm SiO2/Si for optical identification of 2D flakes. As shown in Fig. 1, the optimized Al2O3/ITO/SiO2 stack with the transparent ITO working as the back-gate electrode significantly enhanced the gate control as well as light sensing capabilities. We also studied the 1/f noise characteristics and the application of the stack engineering in MoS2 non-volatile memory and steep-slope negative capacitance transistors (Fig. 2 and 3). This work shows that our engineered stack is an attractive platform to study the physical properties and electronic device applications of the novel 2D materials.