Effects of the Variation of ${V}_{\text {GS}}$ Sweep Range on the Performance of Negative Capacitance FETs

Abstract

We report the first investigation of the impacts of gate voltage sweep range ${V}_{\text {GS,range}}$ on the performance of negative capacitance (NC) transistors. As ${V}_{\text {GS,range}}$ is reduced, NC GeSn pFETs generally exhibit an increased hysteresis or a transition from non-hysteretic to hysteretic, and show a degradation of ${I}_{\text {DS}}$ . This is due to the reduction of the ratio of remnant polarization ${P}_{\text {r}}$ to coercive field ${E}_{\text {c}}$ with the reduced voltage across the HZO. Interestingly, however, some NC devices show a negligible impact of ${V}_{\text {GS,range}}$ on hysteresis and ${I}_{\text {DS}}$ . The NC transistor demonstrates a stable hysteresis in 139–149 mV range and the improved SS and ${I}_{\text {DS}}$ over the control device, with a reduced ${V}_{\text {GS,range}}$ of 0.5 to −0.5 V. To obtain device performance independent of ${V}_{\text {GS,range}}$ , the ratio of ${P}_{\text {r}}/{E}_{\text {c}}$ of the HZO needs to stabilize in a very small ${V}_{\text {GS,range}}$ .