Negative Capacitance Transistor Research Articles

LoGHeD: an effective approach for negative differential resistance effect suppression in negative-capacitance transistors

A negative capacitance transistor with fully depleted silicon-on-insulator (FDSOI) technology (NC-FDSOI) is one of the promising candidates for next-generation low-power devices. However, it suffers from the inherent negative differential resistance (NDR) effect, which is very detrimental to device and circuit designs. Aiming at overcoming this shortcoming, this paper proposes for the first time to use local Gaussian heavy doping technology (LoGHeD) in the channel near the drain side to suppress the NDR effect in the NC-FDSOI. The technical computer-aided design simulation results have validated that the output conductance (G DS) with LoGHeD, which is used to measure the NDR effect, increases compared to the conventional NC-FDSOI counterpart and approaches zero. With the increase in doping concentration, the inhibitory capability of the NDR effect shows a monotonously increasing trend. In addition, the proposed approach maintains and even enhances performances of the NC-FDSOI transistor regarding the electrical parameters, such as threshold voltage (V TH), sub-threshold swing, switching current ratio (I ON/I OFF), and drain-induced barrier lowering.

Toward negative capacitance electronics

Progress in electronics is limited by power dissipation constraints. Ferroelectric materials with a negative capacitance could help to overcome these limits. Especially, HfO2 and ZrO2 based ferroelectrics are promising for negative capacitance electronics due to their compatibility with modern transistor manufacturing processes. Recently, first negative capacitance transistors have been demonstrated. However, further investigations on the microscopic origin of negative capacitance in HfO2- and ZrO2-based ferroelectrics are needed. Lastly, opportunities for negative capacitance beyond transistors are discussed.

Reliability physics of ferroelectric/negative capacitance transistors for memory/logic applications: An integrative perspective

Despite the remarkable development in ferroelectric HfO2-based FETs, key reliability challenges (e.g., retention, endurance, etc.) may still limit their widespread adoption in memory and logic applications. In this paper, we present a simple theoretical framework—based on the Landau theory of phase transition—to design both ferroelectric FETs (FeFETs) and negative capacitance transistors (NCFETs) and investigate their reliability issues. For FeFETs, we analyze the role of interface and bulk traps on memory window closure to quantify endurance under different operating conditions. For NCFETs, we discuss the beneficial role of NC effect in reducing (or even eliminating) the persistent reliability issue of negative bias temperature instability that has plagued MOSFETs for decades. FE/NCFETs can also be affected by the Hot Atom Damage involving switching-induced bond dissociation during transient overshoot. We conclude by discussing how other FET reliability issues (e.g., TDDB, HCD, etc.) may also have to be reinterpreted for FE/NCFETs.

(Invited) Ultrathin Ferroelectric on Silicon and Application for Energy Efficient Logic and Memory Devices

Compared to archetypical perovskites, fluorite HfO2 based ferroelectric materials are process-compatible with advanced CMOS transistors. As a result, they promise to bring ferroelectric technologies into wide-spread applications. At the same time, ferroelectricity in these materials is also different. In conventional perovskites, the polarization becomes weaker as the thickness is decreased due to ‘size effects’. Balking this conventional trend, our recent work has shown that ferroelectricity in HfO2 in fact enhances as the thickness goes down. The ferroelectricity can be demonstrated even in a 1 nm film, which is just two unit cells! In this seminar I shall discuss these results. In addition, I shall also discuss Negative Capacitance transistors with just 18A thick ferroelectric material- the same thickness of high- dielectric used in today’s advanced transistors. I shall further present ferroelectric tunnel junction results with 1 nm ferroelectric. These results demonstrate that, unlike conventional ferroelectrics, thickness scaling is not a bottleneck for HfO2 based ferroelectrics, paving the way for their integration in the most advanced logic and memory devices.

Au/CdBr2/SiO2/Au Straddling‐Type Heterojunctions Designed as Microwave Multiband Pass Filters, Negative Capacitance Transistors, and Current Rectifiers

Herein, SiO2 nanosheets with thicknesses of 25−100 nm are used to enhance the performance of Au/CdBr2 Schottky barriers. The Au/CdBr2/SiO2/Au straddling‐type heterojunction devices are prepared by the thermal evaporation technique. It is observed that SiO2 layers enhance the crystallinity of CdBr2 through increasing the crystallite sizes and decreasing the defect density, stacking faults, and microstrain by 50%, 56%, 32%, and 34%, respectively. A work function of 6.38 eV is determined from the temperature‐dependent electrical resistivity measurements of type CdBr2. In addition, it is observed that, when coated with 50 nm‐thick SiO2, the Au/CdBr2/SiO2/Au straddling‐type transistors can reveal high current rectification ratios of 6.9 × 102 at low biasing voltages in the range of 0.06−0.30 V. The alternating current signals’ analysis in the microwave range of spectra indicates that the current conduction mechanism is dominated by the correlated barrier hopping and quantum mechanical tunneling. It is observed that the Au/CdBr2/SiO2/Au devices exhibit a negative effect accompanied with resonance−antiresonance in the capacitance spectra. Moreover, the microwave cutoff frequency which reaches ≈165.1 GHz and the magnitude of reflection coefficient spectra show that the device under study can perform as multiband pass/stop filters suitable for wire/wireless communication applications including 3G/4G technologies.

Investigation of Trap-Induced Performance Degradation and Restriction on Higher Ferroelectric Thickness in Negative Capacitance FDSOI FET

Bias Temperature Instability (BTI) has always been a critical reliability issue in a field effect transistor (FET). In a negative capacitance (NC) FET, a study of BTI with considering the traps at different interfaces is needed to investigate the device performance, which is not yet explored. In this work, for the first time, we have addressed the individual and the combined effect of bulk traps and the interface traps introduced at different interfaces in an NC fully depleted silicon on insulator (FDSOI) FET. We found: 1) interface Si–SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> –HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> or bulk HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> traps nullify the threshold voltage variation and 2) the presence of traps changes the ferroelectric (FE) polarization and in turn vertical field distribution which leads to an increased OFF current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle OFF}}$ </tex-math></inline-formula> ). Further, it causes the early end of lifetime (EOL) due to bulk HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , and HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> –SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> traps for NC FDSOI. These results have been extracted by using a well-calibrated TCAD framework. Since the current amplification and the subthreshold reduction in NC transistors can be achieved by increasing the FE thickness; but in our work, we found that increasing the thickness is not appropriate as the higher FE thickness predominantly degrades the NC device performance, and a thickness optimization is highly required from the reliability perspective.

Tuning Negative Capacitance in PbZr0.2Ti0.8O3/SrTiO3 Heterostructures via Layer Thickness Ratio

In this work, we exploit the ferroelectric-dielectric layer thickness ratio r as an effective tuning parameter to control the ferroelectric polarization and transient negative capacitance (NC) state in epitaxial ${\mathrm{Pb}\mathrm{Zr}}_{0.2}{\mathrm{Ti}}_{0.8}{\mathrm{O}}_{3}/{\mathrm{Sr}\mathrm{Ti}\mathrm{O}}_{3}$ bilayer heterostructures. The remnant polarization decreases monotonically with decreasing r, with the system exhibiting an abrupt transition from ferroelectric to dielectric dominated behavior at a critical ratio ${r}_{c}$ of 8 to 7, which is consistent with the evolution of the free-energy profile modeled via Landau theory. For samples with large r, the polarization switching dynamics during the transient NC regime can be well described by the nucleation and growth model, with the narrow distribution of the characteristic switching time (${t}_{0}$) pointing to a domain-wall-motion-limited behavior. Right below ${r}_{c}$, we observe a significantly broadened distribution of ${t}_{0}$, which can be attributed to the emergence of a multidomain state. The transient NC mode is quenched in samples with r 6, confirming that the ferroelectric order is suppressed. Our study provides critical information for optimizing the materials design for complex oxide-based NC transistors, paving the path for their application in low-power nanoelectronics.

Insights into unconventional behaviour of negative capacitance transistor through a physics-based analytical model

The present work investigates key attributes of metal–ferroelectric–metal–insulator–semiconductor (MFMIS) cylindrical nanowire (NW) transistor through a physics-based analytical model. The proposed NW MFMIS negative capacitance model is developed by solving the baseline short channel NW model coupled with one-dimensional Landau’s equation while considering the radial dependency of electric field in the ferroelectric, a key feature for NW architecture. Contrary to the expected behaviour of a short channel MOSFET, the analytical framework successfully captures the unconventional effects such as an increase in the threshold voltage, lowering of subthreshold swing, and a negative value of drain-induced barrier lowering with gate length downscaling in MFMIS cylindrical NW devices. Also, the impact of ferroelectric thickness, spacer induced polarization charge density, remnant polarization and coercive field on the unconventional short channel effects have been examined. The influence of different ferroelectric materials (Al–HfO2, Gd–HfO2, Y–HfO2, and HZO) on the extent of internal amplification has also been investigated. The developed model provides new insights into the functioning and optimization of NW MFMIS architecture for facilitating hysteresis-free high internal voltage amplification with sub-60 mV/decade swing.

A Dynamic Current Model for MFIS Negative Capacitance Transistors

A dynamic current model for the double gate negative capacitance field-effect transistor (NCFET) of the metal-ferroelectric-insulator-semiconductor (MFIS) structure is presented in this work. With a damping parameter ρ in the Landau-Khalatnikov (LK) theory for general ferroelectric (FE) materials, the gate control equation of NCFET is intrinsically dynamic which is solved directly as a basis of NCFET modeling. With the time-dependent charge densities at the source and drain sides, a dynamic current model is formulated analytically for the first time, considering the dynamic terms in a self-consistent way. The model has been verified with numerical TCAD simulations. It accurately reproduces the static negative capacitance (NC) effect in enhancing the driving current, as well as the dynamic NC effect, in the conduction delay and hysteresis for a wide range of NCFET parameters. The dynamic model after implementations is successfully applied to circuit simulations such as ring oscillators without convergence issues.

Simulation and Modeling of Novel Electronic Device Architectures with NESS (Nano-Electronic Simulation Software): A Modular Nano TCAD Simulation Framework

The modeling of nano-electronic devices is a cost-effective approach for optimizing the semiconductor device performance and for guiding the fabrication technology. In this paper, we present the capabilities of the new flexible multi-scale nano TCAD simulation software called Nano-Electronic Simulation Software (NESS). NESS is designed to study the charge transport in contemporary and novel ultra-scaled semiconductor devices. In order to simulate the charge transport in such ultra-scaled devices with complex architectures and design, we have developed numerous simulation modules based on various simulation approaches. Currently, NESS contains a drift-diffusion, Kubo–Greenwood, and non-equilibrium Green’s function (NEGF) modules. All modules are numerical solvers which are implemented in the C++ programming language, and all of them are linked and solved self-consistently with the Poisson equation. Here, we have deployed some of those modules to showcase the capabilities of NESS to simulate advanced nano-scale semiconductor devices. The devices simulated in this paper are chosen to represent the current state-of-the-art and future technologies where quantum mechanical effects play an important role. Our examples include ultra-scaled nanowire transistors, tunnel transistors, resonant tunneling diodes, and negative capacitance transistors. Our results show that NESS is a robust, fast, and reliable simulation platform which can accurately predict and describe the underlying physics in novel ultra-scaled electronic devices.

Stability and [formula omitted] analysis of ferroelectric negative capacitance FinFET based SRAM in the presence of variability

For the first time, we analyse SRAM cells made of ferroelectric based negative capacitance (NC) FinFETs considering both global and local variability via Monte-Carlo circuit simulations. First we compare and explain the impact of variability on the device characteristics and the extracted figures of merit of conventional and NC transistors. Then we show that suppressed relative variability in NCFETs leads to lowering of the static Vmin (minimum supply voltage needed for SRAM operation) compared to conventional FinFET based SRAM. We use a physics based compact model for negative capacitance FinFETs realized by a self-consistent coupling of the standard BSIM-CMG compact model for FinFETs with the Landau-Khalatnikov (L-K) model of ferroelectrics. We demonstrate that on including the variability in the ferroelectric thickness and material parameters as well, the advantage of NCFETs diminishes. For the baseline FinFET, we have used model cards from a freely available predictive process design kit (PDK) for the 7 nm technology node where the parameters are optimized for SRAM applications.

On the Resiliency of NCFET Circuits Against Voltage Over-Scaling

Approximate computing is established as a design alternative to improve the energy requirements of a vast number of applications, leveraging their intrinsic error tolerance. Voltage over-scaling (VOS) is one of the most energy-efficient approximation techniques, but its exploitation is still limited due to the large errors it induces. In this work, we investigate, for the first time, the resiliency of negative capacitance transistor (NCFET) technology to VOS in comparison to conventional CMOS technology. Our work reveals that circuits implemented using the NCFET technology exhibit much less timing errors under VOS due to the inherent voltage amplification provided by the ferroelectric layer. NCFET is one of the very promising emerging technologies that is rapidly evolving for low-power circuit as it enables the transistors to switch faster without the need to increase the voltage. We demonstrate how NCFET technology allows circuit designers to effectively employ VOS to boost the efficiency of their approximate circuits, while still keeping the induced errors marginal. Our analysis shows that the VOS-resilience of NCFET circuits enables maximizing the voltage decrease and thus, NCFET based VOS approximate circuits achieve from 1.83× up to 2.78× higher energy reduction compared to the corresponding FinFET circuits for the same error bounds.

Energy Storage and Reuse in Negative Capacitance

In this article, we analyze how a ferroelectric (FE) acts as a rechargeable energy storage medium which stores, releases, and retrieves energy, and helps the gate achieve a desired charge density with reduced energy (voltage) from the external gate drive. During transistor turn-on, the FE releases energy, while the whole system is absorbing energy, and during turn-off, the FE retrieves energy, while the whole system is releasing energy. Capacitor energy is analyzed using two different approaches: static material free energy integrals and transient circuit power integrals. The two results agree within 1%. Energy analysis is also performed for a metal–oxide–semiconductor field-effect transistor structure for two gate lengths, 20 nm and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2~\mu \text{m}$ </tex-math></inline-formula> , in an inverter circuit. At 2- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> gate length, the values of energy match under these two different approaches with less than a 6% difference. The difference is larger in the 20-nm gate length case due to larger parasitic capacitances, such as gate-to-drain and gate-to-source capacitance, affecting the transient circuit analysis. Even so, most of the energy storage and retrieval benefit is retained even in small size negative capacitance transistors.

Negative drain-induced barrier lowering and negative differential resistance effects in negative-capacitance transistors

In this study, the negative drain-induced barrier lowering (DIBL) and negative differential resistance (NDR) effects are investigated in detail in negative-capacitance field-effect transistors (NCFETs) with a fully depleted silicon-on-insulator structure. We show that the negative DIBL and NDR effects are caused by a decrease in the internal gate voltage, which is closely related to the matching between the ferroelectric capacitance and the total gate capacitance of the underlying FET. Further, we define the remnant-polarization-to-coercive-field ratio (RPE), which can be directly used as a parameter to quantify the DIBL effect and describe the sign of the NDR effect. DIBL tends to be consistent with the same RPE, despite exhibiting different current intensities in the strong inversion region. With regard to different RPE, the DIBL effect decreases but the NDR effect increases as RPE decreases. Our work may provide further insight for NCFET designers to adjust capacitance matching to optimize the DIBL and NDR effects.

On the Critical Role of Ferroelectric Thickness for Negative Capacitance Device-Circuit Interaction

This paper demonstrates the critical role that Ferroelectric (FE) layer thickness (tFE) plays in Negative Capacitance (NC) transistors connecting device and circuit levels together. The study is done through fully-calibrated TCAD simulations for a 14nm FDSOI technology node, exploring the impact of tFE on the figures of merit of n-type and p-type devices, voltage transfer characteristic (VTC) and noise margin of inverter as well as the speed of buffer circuits. First, we analyze the device electrical parameters (e.g., ION, SS, ION/IOFF and Cgg) by varying tFE up to the maximum level at which hysteresis in the I-V characteristic starts. Then, we analyze the deleterious impact of Negative Differential Resistance (NDR), due to the drain to gate coupling, demonstrating how it imposes an additional constraint limiting the maximum tFE. We show the consequences of NDR effects on the VTC and noise margin of inverter, which are essential components for constructing robust clock trees in any chip. We demonstrate how the considerable increase in the gate’s capacitance due to FE seriously degrades the circuit’s performance imposing further constraints limiting the maximum tFE. Further, we analyze the impact of tFE on the SRAM cell static performance metrics such hold noise margin (HNM), read noise margin (RNM) and write noise margin (WNM) at supply voltages of 0.7V and 0.4V. We demonstrate that the HNM and RNM in a NC-FDSOI FET based SRAM cell are higher then those of the baseline FDSOI FET based SRAM cell noise margin and further increase with tFE. However, the WNM in general follows a non monotonic trend w.r.t tFE, and the trend also depends on the supply voltage. Finally, we optimize the design of the SRAM cell considering overall performance metrics. All in all, our analysis provides guidance for device and circuit designers to select the optimal FE thickness for NCFETs in which hysteresis-free operations, reliability, and performance are optimized.

Power Side-Channel Attacks in Negative Capacitance Transistor

Side-channel attacks have empowered bypassing of cryptographic components in circuits. Power side-channel (PSC) attacks have received particular traction, owing to their non-invasiveness and proven effectiveness. Aside from prior art focused on conventional technologies, this is the first work to investigate the emerging Negative Capacitance Transistor (NCFET) technology in the context of PSC attacks. We implement a CAD flow for PSC evaluation at design-time. It leverages industry-standard design tools, while also employing the widely-accepted correlation power analysis (CPA) attack. Using standard-cell libraries based on the 7nm FinFET technology for NCFET and its counterpart CMOS setup, our evaluation reveals that NCFET-based circuits are more resilient to the classical CPA attack, due to the considerable effect of negative capacitance on the switching power. We also demonstrate that the thicker the ferroelectric layer, the higher the resiliency of the NCFET-based circuit, which opens new doors for optimization and trade-offs.

Analog and RF performance evaluation of negative capacitance SOI junctionless transistor

In this work, for the first time, the DC characteristics and Analog/RF performance of negative capacitance (NC) Silicon-on-insulator (SOI) junctionless transistor (JLT) have been investigated including quantum confinement effects. In NC transistors, ferroelectric materials are used in the gate-stack to improve the switching characteristics. The Metal-Ferroelectric-Metal-Insulator-semiconductor (MFMIS) gate-stack structure has been simulated with the help of 1D Landau Khalatnikov (LK) equation to incorporate the effect of negative capacitance with SOI JLT. The impact of varying the temperatures in the range 300–380 K and ferroelectric layer thickness (tf) of 0 to 4.5 nm on the device characteristics are studied. The analog and RF characteristics such as transconductance (gm) and cut-off frequency (ft) of NC SOI JLT show better performance over SOI JLT. A minimum subthreshold swing (SS) of 12.77 mV/decade and ft of 590 GHz has been observed at 300 K for a channel length (L) of 14 nm with tfof 4.5 nm. The characteristics of NC SOI JLT are evaluated by coupling the 1D LK equation with the simulated results of SOI JLT which are obtained using 2D device simulator AtlasTM from Silvaco.

High performance negative capacitance field-effect transistor featuring low off-state current, high on/off current ratio, and steep sub-60 mV dec−1 swing

In this work, we demonstrated that the 5-nm-thick HfAlOx negative capacitance transistor (NCFET) with optimized Al doping can achieve a minimum 33 mV dec−1 subthreshold swing (SS), an ultralow Ioff of 7.44 fA μm−1, and a high Ion/Ioff ratio of 1.9 × 108. The NC switching with sub-60 mV dec−1 SS can be implemented from VDS = 0.2 V to 0.8 V due to an ultralow off-state leakage current. The experimental results reveal that well-controlled Al doping in HfAlOx not only reduces off-state leakage of the transistor, but also improves the ferroelectric NC effect to achieve a sub-60 mV dec−1 switching under a favorably low sub-1 voltage. This scaled HfAlOx NCFET with optimized Al doping and fluorine defect passivation shows the great potential for the application of low power logic devices.

Impact of Interface Traps on Negative Capacitance Transistor: Device and Circuit Reliability

In this work, we investigate the impact of Si-SiO2 interface traps on the performance of negative capacitance transistor, which is a promising emerging technology that aims at achieving a steep sub-threshold slope. Interface traps induced degradation is well known to be one of the major concerns when it comes to reliability. We focus on investigating the impact of different interface trap concentrations on the figures of merit of both the devices and circuits. Our investigation is performed using TCAD models, which are well calibrated against 14nm production quality FinFETs. This allows accurate analysis and modeling of the impact of NC on the electric field across the SiO2 layer. Then, the industry compact model of FinFET (BSIM-CMG) is fully calibrated to reproduce TCAD data. In addition, a physics-based NC model is integrated and solved self-consistently within the BSIM-CMG model in which TCAD data of NC-pFinFETs and NC-nFinFETs are also well matched. This allows studying how interface traps induced degradation can impact circuits. Our results demonstrate that the amplified electric field across the SiO2 layer within NC-pFinFET due to NC effect leads to a higher interface trap concentration. This, in turn, results in a larger degradation in the NC-pFinFET compared to its pFinFET counterpart – when both of these devices are operated at the same nominal supply voltage of the 14nm node. However, at the same interface trap concentration, the NC-pFinFET always exhibits less degradation than the baseline pFinFET due to the former’s better electrostatic integrity on account of voltage amplification effect. With respect to circuits, we study both Ring Oscillator (RO) and 6-T SRAM cell circuits. We show how the frequency of RO in the case of NC-FinFET is always less impacted by interface trap induced degradations compared to its counterpart FinFET-based RO. For 6-T SRAM cell, we demonstrate how the key reliability metrics such as hold noise margin, read noise margin, and write noise margin are also less impacted by the induced degradations in NC-FinFET SRAMs compared to the baseline FinFET SRAMs. This is because of the much better electrostatic integrity that NC provides.

Excellent Ferroelectric Properties of Hf0.5Zr0.5O2 Thin Films Induced by Al2O3 Dielectric Layer

The ferroelectricity of Hf0.5Zr0.5O2 (HZO) thin films has been usually reported to be induced by metallic capping layer. In this work, we successfully obtained ferroelectricity of HZO thin films induced by ultrathin insulating Al2O3 capping layers. The ferroelectric properties of HZO thin films induced by Al2O3 capping layers with different thickness have been investigated. It was found that the Al2O3(2 nm)/HZO (20 nm) stack shows excellent ferroelectric properties. The Au/Al2O3(2 nm)/HZO (20 nm)/TiN capacitor exhibits a very low leakage current of $\sim {4.2}\times {10}^{\text {-9}}$ A at 4 V and a maximum $2{P}_{r}\approx 32.3~\mu \text{C}$ /cm2 at sweeping voltages between ±8 V. In addition, the capacitor also shows excellent endurance properties up to 108 cycles. Our work demonstrated that dielectric films like Al2O3 can be adopted to be used as capping layer to generate excellent ferroelectric properties of HfO2-based thin films, which will contribute to their future applications in ferroelectric memory and negative capacitance transistors.