Investigation of Trap-Induced Performance Degradation and Restriction on Higher Ferroelectric Thickness in Negative Capacitance FDSOI FET

Abstract

Bias Temperature Instability (BTI) has always been a critical reliability issue in a field effect transistor (FET). In a negative capacitance (NC) FET, a study of BTI with considering the traps at different interfaces is needed to investigate the device performance, which is not yet explored. In this work, for the first time, we have addressed the individual and the combined effect of bulk traps and the interface traps introduced at different interfaces in an NC fully depleted silicon on insulator (FDSOI) FET. We found: 1) interface Si–SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> –HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> or bulk HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> traps nullify the threshold voltage variation and 2) the presence of traps changes the ferroelectric (FE) polarization and in turn vertical field distribution which leads to an increased OFF current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle OFF}}$ </tex-math></inline-formula> ). Further, it causes the early end of lifetime (EOL) due to bulk HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , and HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> –SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> traps for NC FDSOI. These results have been extracted by using a well-calibrated TCAD framework. Since the current amplification and the subthreshold reduction in NC transistors can be achieved by increasing the FE thickness; but in our work, we found that increasing the thickness is not appropriate as the higher FE thickness predominantly degrades the NC device performance, and a thickness optimization is highly required from the reliability perspective.